Optical encoder with a current regulating circuit for a light emitter
View Patent ↗An LED current regulator can regulate an LED current of an encoder system. The LED current regulator may comprise a first analog multiplier and a second analog multiplier. Each of the first and second analog multipliers may be configured to receive respective photodetector output signals, characterized by a peak-to-peak voltage, Vpp, and may be configured to generate respective first and second multiplier output signals. The first and second multiplier output signals may be combined to produce a first DC level, which may be representative of the peak-to-peak voltage, Vpp, of the photodetector output signals.
1. A light emitter regulating circuit for a light emitter of an optical encoder system comprising:
a first analog multiplier and a second analog multiplier configured to receive output signals generated by light detectors of the encoder system;
a third analog multiplier to receive a peak reference input voltage;
a Direct Current (DC) level generator to generate a first Direct Current (DC) offset level;
a Direct Current (DC) offset detector to receive the first DC offset level and the peak reference voltage to generate an offset voltage value; and
a light emitter regulation voltage generator configured to receive the offset voltage value and a light emitter reference voltage to generate a light emitter regulation voltage.
2. The light emitter regulating circuit of claim 1 , wherein the first analog multiplier is configured to receive two sine signals to generate a first multiplier output signal, and wherein the first multiplier output signal comprises a sine squared (“Si{circumflex over (n)}2”) signal.
3. The light emitter regulating circuit of claim 1 , wherein the second analog multiplier is configured to receive two cosine signals to generate a second multiplier output signal, and wherein the second multiplier output signal comprises of a cosine squared (“Coŝ2”) signal.
4. The light emitter regulating circuit of claim 1 , wherein:
the first analog multiplier is configured to generate a first multiplier output signal;
the second analog multiplier is configured to generate a second multiplier output signal; and
the DC level generator is configured to combine the first and the second multiplier output signals to generate the first DC offset level.
5. The light emitter regulating circuit of claim 1 , wherein the light emitter regulating circuit is configured to regulate the light emitter of the optical encoder in a substantially real time manner.
6. An optical encoder, comprising:
a first analog multiplier;
a second analog multiplier;
a Direct Current (“DC”) level generator to generate a first Direct Current (“DC”) offset level;
a Direct Current (“DC”) offset detector to receive the first DC offset level and a peak reference voltage to generate an offset voltage value; and
a light emitter voltage generator configured to receive the offset voltage value and a light emitter reference voltage to generate a light emitter regulation voltage.
7. The optical encoder of claim 6 , wherein the first analog multiplier is configured to receive a sinusoidal input signal, and wherein the first analog multiplier is configured to generate a sine squared (“Si{circumflex over (n)}2”) signal in response to the sinusoidal input signal.
8. The optical encoder of claim 7 , wherein the second analog multiplier is configured to receive a cosinusoidal input signal, and wherein the second analog multiplier is configured to generate a cosine squared (“Coŝ2”) signal in response to the cosinusoidal input signal.
9. The optical encoder of claim 8 , wherein the DC level generator is configured to combine the sine squared signal and the cosine squared signal to generate the first DC offset level.
10. An optical encoder, comprising:
a light emitter;
an encoder element having a plurality of apertures;
a light detector optically coupled with the light emitter through the encoder element to receive light transmitted through the plurality of apertures;
a first analog multiplier and a second analog multiplier coupled to the light detector;
a summing circuit coupled to the first and second analog multiplier, the summing circuit configured to generate an offset signal;
a comparator configured to substantially determine a voltage difference between the offset signal and a peak reference signal, and in response thereto, generate a light emitter regulating signal; and
an amplifier coupled to the comparator to receive the light emitter regulating signal, wherein the amplifier is configured to regulate the light emitter in response to the light emitter regulating signal.
11. The optical encoder of claim 10 , wherein:
the light detector is configured to generate a sinusoidal detector signal and a cosinusoidal detector signal;
the first and second analog multipliers configured to generate a sine squared signal and a cosinusoidal squared signal from the sinusoidal detector signal and the cosinusoidal detector signal; and
the summing circuit configured to generate the offset signal from the sine squared signal and the cosinusoidal squared signal.
12. The optical encoder of claim 10 , further comprising a first circuit configured to convert the voltage difference into a current to regulate the light emitter.
13. The optical encoder of claim 10 , wherein:
the first analog multiplier is configured to generate a DC offset output;
the first analog multiplier is coupled to at least one reference signal as input to the first analog multiplier; and
the first analog multiplier is configured to compare the at least one reference signal and the DC offset output.
14. The optical encoder of claim 10 further comprising a peak reference source configured to generate a peak reference input voltage.
15. The optical encoder of claim 14 further comprising a third analog multiplier circuit configured to generate the peak reference signal, as input to the comparator in response to the peak reference input voltage.
16. The optical encoder of claim 15 , wherein the first and second analog multipliers have a first process offset, and wherein the third analog multiplier circuit is configured to provide a second process offset that substantially tracks the first process offset.
17. The optical encoder of claim 15 , wherein the first and second analog multipliers have a first thermal offset, and wherein the third analog multiplier circuit is configured to provide a second thermal offset that substantially tracks the first thermal offset.
18. The optical encoder of claim 14 , wherein the light detector is configured to generate a sinusoidal detector signal and a cosinusoidal detector signal, and wherein the peak reference source is configured to generate the peak reference input voltage corresponding to a substantially ideal peak-to-peak voltage of the sinusoidal detector signal and the cosinusoidal detector signal generated under a substantially ideal condition.
19. The optical encoder of claim 10 , wherein the light detector is configured to generate sinusoidal output signals, and wherein the summing circuit is configured to generate a first DC offset signal that is substantially representative of a peak-to-peak voltage of the sinusoidal output signals of the light detector.
20. The optical encoder of claim 10 further comprising a voltage generator configured to convert the light emitter regulating signal into current that regulates the light emitter.