Electronic device and method for a limiter in an AC application
View Patent ↗An electronic device, including a first limiter including a first transistor configured to be coupled with a first side of a channel to a first output node of a non-ideal voltage source having an inner impedance greater zero in order to limit the voltage at the first output node by drawing a current from the first output node. The second side of the channel of the first transistor is coupled to a capacitor so as to supply a current from the first output node to the capacitor, if the voltage level at the output node reaches or exceeds an upper limit.
1. An electronic device comprising:
a first limiter including a first transistor configured to be coupled with a first side of a channel to a first output node of a non-ideal voltage source having an inner impedance greater zero in order to limit the voltage at the first output node by drawing a current from the first output node, wherein the second side of the channel of the first transistor is coupled to a capacitor so as to supply a current from the first output node to the capacitor, if the voltage level at the output node reaches or exceeds an upper limit, wherein the first limiter further comprises a second transistor configured to be coupled with a first side of a channel to a second output node of a second non-ideal voltage source in order to limit the voltage at the second output node, wherein the second side of the channel of the second transistor is coupled to the capacitor so as to supply a current from the capacitor to the second output node, if the voltage level at the second output node reaches or exceeds a lower limit.
2. An electronic device comprising:
a first limiter including a first transistor configured to be coupled with a first side of a channel to a first output node of a non-ideal voltage source having an inner impedance greater zero in order to limit the voltage at the first output node by drawing a current from the first output node, wherein the second side of the channel of the first transistor is coupled to a capacitor so as to supply a current from the first output node to the capacitor, if the voltage level at the output node reaches or exceeds an upper limit, wherein the first limiter further comprises a second transistor configured to be coupled with a first side of a channel to the first output node in order to limit the voltage at the first output node, wherein the second side of the channel of the second transistor is coupled to the capacitor so as to supply a current from the capacitor to the first output node, if the voltage level at the output node reaches or exceeds a lower limit.
3. The electronic device according to claim 1 , further comprising a second limiter coupled to the capacitor for limiting the voltage across the capacitor.
4. The electronic device according to claim 1 , wherein the first transistor is a PMOS transistor and the second transistor is a NMOS transistor.
5. The electronic device according to claim 1 , wherein the first transistor is a PNP transistor and the second transistor is an NPN transistor.
6. The electronic device according to claim 1 , wherein the inner resistive impedance is chosen from the equations:
R<T|VL 1 −V BUF|/| Q 1 −Q 2|
and
R<T|VL 2 −V BUF|/| Q 1 −Q 2|
where R (=Z) is the output impedance of the buffer BUF, T is the period of the alternating voltage of the AC voltage source VCS 3 (T=1/f), VL 1 is the upper limit and VL 2 is the lower limit for the alternating voltage, Q 1 is the charge of the first half cycle and Q 2 is the charge of the second half cycle.
7. A method of limiting a voltage of a non-ideal voltage source, the method comprising:
drawing a current from a first output node of the voltage source through a first transistor in order to limit a voltage level at the first output node to an upper limit;
feeding the current to a capacitor for storing a charge; and
feeding a charge stored on the capacitor back through a second transistor to so as to limit a voltage level if the voltage level reaches or exceeds a lower limit, wherein the charge stored on the capacitor is fed back to the first output node.
8. The electronic device according to claim 2 , further comprising a second limiter coupled to the capacitor for limiting the voltage across the capacitor.
9. The electronic device according to claim 2 , wherein the first transistor is a PMOS transistor and the second transistor is a NMOS transistor.
10. The electronic device according to claim 2 , wherein the first transistor is a PNP transistor and the second transistor is an NPN transistor.
11. The electronic device according to claim 2 , wherein the inner resistive impedance is chosen from the equations:
R<T|VL 1 −V BUF|/| Q 1 −Q 2|
and
R<T|VL 2 −V BUF|/| Q 1 −Q 2|
where R (=Z) is the output impedance of the buffer BUF, T is the period of the alternating voltage of the AC voltage source VCS 3 (T=1/f), VL 1 is the upper limit and VL 2 is the lower limit for the alternating voltage, Q 1 is the charge of the first half cycle and Q 2 is the charge of the second half cycle.