Micro-fluidic test apparatus and method

1. An apparatus for determining an osmolarity of a fluid, comprising:

a micro-fluidic circuit disposed in a chip, the micro-fluidic circuit comprising a tunnel, a larger hole overlapping a smaller hole at a first end of the tunnel, and a vent hole at a second end of the tunnel; and

an electrical circuit formed in the chip and in communication with the micro-fluidic circuit configured for determining the osmolarity of the fluid contained within the micro-fluidic circuit,

wherein the electrical circuit comprises a first electrode disposed in the tunnel at a first downstream location along the tunnel and a second electrode disposed in the tunnel at a second downstream location along the tunnel,

wherein the electrical circuit comprises:

first and second vias formed on either side of the tunnel at the first downstream location and electrically connected to the first electrode;

third and fourth vias formed on either side of the tunnel at the second downstream location and electrically connected to the second electrode; and

fifth and sixth vias within a perimeter of the smaller hole when viewed in a top view;

wherein the third via is electrically connected to the fifth via to measure an electrical property of a fluid sample between the fifth via and the second electrode; and

the second via is electrically connected to the sixth via to measure the electrical property of the fluid sample between the sixth via and the first electrode,

further comprising a device connected to the electrical circuit, the device being configured to determine the osmolarity of the fluid sample in the micro-fluidic circuit based on the electrical property of the fluid.

2. The apparatus of claim 1 , wherein the second downstream location is between the first downstream location and the vent hole along the tunnel.

3. The apparatus of claim 2 , wherein:

the micro-fluidic circuit comprises more than one micro-fluidic circuit disposed in the chip, and

the electrical circuit comprises more than one electrical circuit formed in the chip.

4. The apparatus of claim 2 , wherein the chip comprises a layered structure.

5. The apparatus of claim 4 , wherein layers of the layered structure comprise a mixture comprising silica, alumina, and magnesia.

6. The apparatus of claim 4 , wherein the micro-fluidic circuit is formed in at least two layers of the layered structure.

7. The apparatus of claim 4 , wherein:

the large hole and the vent hole are in a first layer of the layered structure; and

the small hole is in a second layer of the layered structure.

8. The apparatus of claim 7 , wherein the electrical circuit comprises electrically conductive material disposed in a third layer of the layered structure.