IP Library Granted Patent US 8,726,102
Granted Patent B2
US 8,726,102 · App. 13/412,037 · Granted May 13, 2014

System and method for handling system failure

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Quick Facts
Patent No.
US 8,726,102
App. No.
13/412,037
Granted
May 13, 2014
Kind
B2
Abstract

A system and a method for handling a system failure are disclosed. The method is adapted for an information handling system having a basic input and output system and a micro-controller. The method includes the following steps: sending, via the micro-controller, a signal; checking, via the micro-controller, whether an acknowledgement is received from the basic input and output system responsive to the signal; and scanning, via the micro-controller, a type of a system failure in response to the acknowledgement being not received.

Claims (23)

1. A method for handling a system failure in an information handling system comprising a basic input and output system and a micro-controller, said method comprising:

sending, via said micro-controller, a signal;

checking, via said micro-controller, whether an acknowledgement is received from said basic input and output system responsive to said signal; and

scanning, via said micro-controller, for a type of a system failure in response to said acknowledgement being not received.

2. The method of claim 1 , wherein said information handling system further comprises a peripheral device, and said scanning step comprises:

scanning, via said micro-controller, a status register corresponding in position to said peripheral device for a failure of said peripheral device; and

storing, upon confirmation that a failure has occurred to said peripheral device, said failure of said peripheral device via said micro-controller.

3. The method of claim 1 , wherein said information handling system further comprises a memory, and said scanning step comprises:

scanning, via said micro-controller, a status register corresponding in position to said memory for a failure of said memory; and

storing, upon confirmation that a failure has occurred to said memory, said failure of said memory via said micro-controller.

4. The method of claim 1 , wherein said information handling system further comprises a processor, and said scanning step comprises:

scanning, via said micro-controller, a status register corresponding in position to said processor for a failure of said processor; and

storing, upon confirmation that a failure has occurred to said processor, said failure of said processor via said micro-controller.

5. The method of claim 1 , further comprising:

marking, in response to a result of said scanning indicates said type of said system failure, said type via said micro-controller; and

restarting said information handling system via said micro-controller.

6. The method of claim 1 , further comprising:

marking, in response to a result of said scanning indicates said type of said system failure, said type via said micro-controller; and

resetting a system configuration file via said basic input and output system according to said type of said mark.

7. The method of claim 1 , wherein said information handling system further comprises a chipset coupled between said basic input and output system and said micro-controller, said method further comprising:

triggering, by said signal, a system management interrupt (SMI) of said chipset;

serving, via a system management interrupt (SMI) handling procedure of said basic input and output system, said system management interrupt (SMI); and

generating, via said system management interrupt (SMI) handling procedure, said acknowledgement.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 10, 2014
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: LENOVO INTERNATIONAL LIMITED
Reel/Frame 034194/0291 →