Semiconductor devices having vertical device and non-vertical device and methods of forming the same

1. A semiconductor device comprising:

a substrate extending in a horizontal direction;

a vertical transistor on the substrate, the vertical transistor comprising:

a first diffusion region on the substrate;

a channel region on the first diffusion region and extending in a vertical direction relative to the horizontal direction of the extension of the substrate;

a second diffusion region on the channel region; and

a gate electrode at a sidewall of, and insulated from, the channel region; and

a horizontal transistor on the substrate, the horizontal transistor comprising:

a first diffusion region and a second diffusion region on the substrate and spaced apart from each other;

a channel region on the substrate between the first diffusion region and the second diffusion region; and

a gate electrode on the channel region and isolated from the channel region;

wherein a portion of a gate electrode of the vertical transistor and a portion of the gate electrode of the horizontal transistor are at a same vertical position in the vertical direction relative to the substrate,

wherein the first diffusion region of the horizontal transistor is contiguous with the first diffusion region of the vertical transistor; and

wherein the first diffusion region of the horizontal transistor that is contiguous with the first diffusion region of the vertical transistor has a lowermost boundary that is higher in vertical position than a lowermost boundary of the first diffusion region of the vertical transistor, relative to an upper surface of the substrate.

2. The semiconductor device of claim 1 further comprising a layer of material on the horizontal transistor and the vertical transistor, the gate electrode of the vertical transistor and the gate electrode of the horizontal transistor both in direct contact with the layer of material.

3. The semiconductor device of claim 2 wherein the layer of material comprises an etch stop layer.

4. The semiconductor device of claim 2 wherein the layer of material comprises an insulating layer.

5. The semiconductor device of claim 1 wherein the gate electrode of the vertical transistor and the gate electrode of the horizontal transistor comprise portions of a same layer of material.

6. The semiconductor device of claim 1 wherein:

the first diffusion region of the vertical transistor comprises a drain of the vertical transistor;

the second diffusion region of the vertical transistor comprises a source of the vertical transistor;

the first diffusion region of the horizontal transistor comprises one of a drain and source of the horizontal transistor; and

the second diffusion region of the horizontal transistor comprises the other of the drain and source of the horizontal transistor.

7. The semiconductor device of claim 1 wherein the first diffusion region of the vertical transistor and the first diffusion region and second diffusion region of the horizontal transistor lie at a same vertical position relative to the substrate.

8. The semiconductor device of claim 1 wherein the first diffusion region of the vertical transistor includes a vertical protrusion extending in the vertical direction, and wherein the vertical channel region is on the vertical protrusion.

9. The semiconductor device of claim 1 wherein the vertical transistor further comprises a silicide region on the second diffusion region.

10. The semiconductor device of claim 9 wherein the vertical transistor further comprises a metal pattern on the silicide region.

11. The semiconductor device of claim 1 wherein the second diffusion region of the vertical transistor comprises a silicide region in direct contact with the vertical channel region of the vertical transistor.

12. The semiconductor device of claim 1 wherein the first diffusion region of the horizontal transistor and the first diffusion region of the vertical transistors both have a silicide region thereon.

13. The semiconductor device of claim 1 further comprising an insulating spacer on sidewalls of the gate electrode of the vertical transistor and on sidewalls of the gate electrode of the horizontal transistor.

14. The semiconductor device of claim 1 further comprising a silicide region on the gate electrode of the vertical transistor and on the gate electrode of the horizontal transistor.

15. The semiconductor device of claim 1 wherein the second diffusion region of the vertical transistor has a width in the horizontal direction that is greater than a width of the channel region of the vertical transistor in the horizontal direction.

16. The semiconductor device of claim 1 further comprising an interlayer via in direct contact with a top of the second diffusion region of the vertical transistor.

17. The semiconductor device of claim 1 further comprising a buried oxide layer on the substrate and wherein the vertical transistor and the horizontal transistor are on the buried oxide layer.

18. The semiconductor device of claim 1 wherein the channel region of the vertical transistor comprises single-crystal material.

19. The semiconductor device of claim 1 wherein the vertical transistor comprises a first vertical transistor, and further comprising:

a second vertical transistor on the substrate, the second vertical transistor comprising:

a first diffusion region on the substrate;

a channel region on the first diffusion region and extending in a vertical direction relative to the horizontal direction of the extension of the substrate;

a second diffusion region on the first vertical channel region; and

a gate electrode at a sidewall of, and insulated from, the vertical channel region.

20. The semiconductor device of claim 19 wherein the first vertical transistor and second vertical transistor comprise an inverter pair.

21. The semiconductor device of claim 19 wherein the first vertical transistor comprises one of a p-channel and n-channel transistor and wherein the second vertical transistor comprise the other of a p-channel and n-channel transistor.

22. The semiconductor device of claim 1 wherein the substrate comprises one of a bulk substrate and a silicon-on-insulator (SOI) substrate.

23. The semiconductor device of claim 1 further comprising an isolation layer on the substrate, wherein top surfaces of the first diffusion region of the vertical transistor, the first and second diffusion regions of the horizontal transistor and the channel region of the horizontal transistor are at a lower level than a top surface of the isolation layer.

24. A semiconductor device comprising:

a substrate extending in a horizontal direction;

a vertical transistor on the substrate, the vertical transistor comprising:

a first diffusion region on the substrate;

a channel region on the first diffusion region and extending in a vertical direction relative to the horizontal direction of the extension of the substrate;

a second diffusion region on the channel region; and

a gate electrode at a sidewall of, and insulated from, the channel region; and

a recess channel transistor on the substrate, the recess channel transistor comprising:

a first diffusion region and a second diffusion region on the substrate and spaced apart from each other;

a channel region on the substrate between the first diffusion region and the second diffusion region; and

a gate electrode on the channel region and isolated from the channel region;

wherein the first diffusion region of the recess channel transistor is contiguous with the first diffusion region of the vertical transistor; and

wherein the gate electrode of the recess channel transistor has a bottom that is at a portion that is lower than a lowermost boundary of the first and second diffusion regions of the recess channel transistor.