Pipelined ADC stage filters
View Patent ↗A pipelined Analog-to-Digital Converter (ADC) stage includes a main sampling path having a first filter in series with a first sample and hold circuit and a sub-ADC sampling path having a second filter in series with a second sample and hold circuit driving a sub-ADC connected to a sub-Digital-to-Analog Converter (DAC). The frequency response of the main sampling path is matched to a frequency response of the sub-ADC sampling path such that a residue signal of the pipelined ADC stage stays within range.
1. A pipelined Analog-to-Digital Converter (ADC) stage comprising:
a main sampling path comprising a first filter in series with a first sample and hold circuit; and
a sub-ADC sampling path comprising a second filter in series with a second sample and hold circuit driving a sub-ADC connected to a sub-Digital-to-Analog Converter (DAC);
wherein a frequency response of said main sampling path is matched to a frequency response of said sub-ADC sampling path such that a residue signal of said pipelined ADC stage stays within range.
2. The pipelined ADC of claim 1 , further comprising a signal input that is connected to multiple filters, said filters being connected to said main sampling path, said sub-ADC sampling path, and bootstrap circuitry, said bootstrap circuitry having outputs connected to said sample and hold circuits within said pipelined ADC stage.
3. The pipelined ADC of claim 2 , wherein said bootstrap circuitry is shared by said first sample and hold circuit and said second sample and hold circuit.
4. The pipelined ADC of claim 2 , wherein said first sample and hold circuit and said second sample and hold circuit utilize different bootstrap circuits.
5. The pipelined ADC of claim 1 , wherein a frequency response of said sub-ADC is not matched with a frequency response of said main sampling path.
6. The pipelined ADC of claim 1 , wherein said main sampling path is configured to sample an input signal in a time-interleaved manner.
7. The pipelined ADC of claim 3 , wherein each sampling circuit of at least one of: said main sampling path and said sub-ADC sampling path uses a different filter.
8. The pipelined ADC of claim 1 , wherein said pipelined ADC is a differential pipelined ADC.
9. The pipelined ADC of claim 1 , wherein sampling of said main sampling path is performed using capacitors of said MDAC.
10. The pipelined ADC of claim 1 , wherein said sampling of said sub-ADC sampling path is performed using capacitors of said sub-ADC.
11. The pipelined ADC of claim 1 , wherein said filters are designed to mitigate an impact of charge injections from said sampling paths.
12. The pipelined ADC of claim 1 , further comprising, bootstrap circuitry connected a sample-and-hold circuit within one of said sampling paths, said bootstrap circuitry utilizing a filter, said filter causing a path through said bootstrap circuitry to have a frequency response that matches said frequency response of said main sampling path.
13. The pipelined ADC of claim 1 , wherein at least one of said filters comprises at least one of: differential components and single-ended components.
14. A method for operating a pipelined Analog-to-Digital Converter (ADC) stage, the method comprising:
sampling an input signal with a main sampling path comprising a first snubbing filter and a Multiplying-Digital-to-Analog Converter (MDAC); and
sampling said input signal with a sub-ADC sampling path comprising a second filter and a sub-ADC connected to said MDAC;
wherein a frequency response of said main sampling path is matched to a frequency response of said sub-ADC sampling path such that a residue signal of said pipelined ADC stage stays within range.
15. The method of claim 14 , wherein a frequency response of said sub-ADC is not matched with a frequency response of said main sampling path.
16. The method of claim 14 , wherein said main sampling path is configured to sample an input signal in a time-interleaved manner.
17. The method of claim 14 , wherein said pipelined ADC is a differential pipelined ADC.
18. The method of claim 14 , wherein sampling of said main sampling path is performed using capacitors of said MDAC.
19. The method of claim 14 , wherein said sampling of said sub-ADC sampling path is performed using capacitors of said sub-ADC.
20. A pipelined Analog-to-Digital Converter (ADC) comprising a number of stages, a first stage comprising:
a signal input connected to a main sampling path comprising a first snubbing filter between said signal input and a Multiplying-Digital-to-Analog Converter (MDAC); and
a sub-ADC sampling path comprising a second filter between said signal input and a sub ADC connected to said MDAC, said sub-ADC sampling path also connected to said signal input;
wherein a frequency response of said main sampling path is matched to a frequency response of said sub-ADC sampling path such that a residue signal of said pipelined ADC stage stays within range and a frequency response of said sub-ADC is not matched with a frequency response of said main sampling path.