Simple fairness protocols for daisy chain interconnects
A method for transmitting packets, including forwarding a first set of upstream packets and a first set of local packets by inserting at least one of the first set of local packets between subsets of the first set of upstream packets according to a first insertion rate; calculating a second insertion rate after forwarding a predetermined number of upstream packets generated by a single upstream source, by dividing a cardinality of the first set of upstream packets by a greatest common divisor of the predetermined number and the cardinality of the first set of upstream packets; and forwarding a second set of upstream packets and a second set of local packets from the local switch to the downstream switch by inserting at least one of the second set of local packets between subsets of the second set of upstream packets according to the second insertion rate.
1. A system for transmitting packets, comprising:
an upstream packet counter (UPC), an upstream packet window counter (UPWC), and a plurality of upstream switch packet counters (USPCs) configured to change in response to forwarding a first set of upstream packets, a second set of upstream packets, and a third set of upstream packets to a downstream switch;
a local packet queue (LPQ) storing a local packet for transmission to the downstream switch after forwarding the first set of upstream packets to the downstream switch and before forwarding the second set of upstream packets to the downstream switch;
a local packet counter (LPC) configured to decrement in response to forwarding the local packet;
a UPWC register for restoring the UPWC before the third set of upstream packets is forwarded to the downstream switch; and
a scheduling engine operatively connected to the UPC, the plurality of USPCs, the UPWC, the UPWC register, and the LPQ, and configured to obtain a sum of the USPCs and set the UPWC register to the sum after performing a plurality of bitwise right shift operations on the sum,
wherein at least one of the plurality of USPCs equals a predetermined value after the first set of upstream packets is forwarded to the downstream switch,
wherein the scheduling engine, the UPC, the plurality of USPCs, the UPWC, the UPWC register, and the LPQ are located on a local switch operatively connected to the downstream switch, and
wherein the first set of upstream packets, the second set of upstream packets, and the third set of upstream packets are generated by at least one upstream source operatively connected to the local switch.
2. The system of claim 1 , further comprising:
a UPC register for restoring the UPC before the third set of upstream packets is forwarded to the downstream switch,
wherein the scheduling engine is further configured to set the UPC register to the sum before the second set of upstream packets is forwarded to the downstream switch.
3. The system of claim 2 , wherein the scheduling engine is further configured to set the UPC to the sum before the second set of upstream packets is forwarded to the downstream switch.
4. The system of claim 2 , further comprising:
a lookup table storing a greatest common divisor of the sum and the predetermined value,
wherein the scheduling engine is further configured to divide the UPC register by the greatest common divisor.
5. The system of claim 1 , further comprising:
a LPC register for restoring the LPC before the third set of upstream packets is forwarded to the downstream switch,
wherein the scheduling engine is further configured to set the LPC register to the predetermined value before the second set of upstream packets is forwarded to the downstream switch.
6. The system of claim 5 , wherein the scheduling engine is further configured to set the LPC to the predetermined value before the second set of upstream packets is forwarded to the downstream switch.
7. The system of claim 5 , further comprising:
a lookup table storing a greatest common divisor of the sum and the predetermined value,
wherein the scheduling engine is further configured to divide the LPC register by the greatest common divisor.
8. The system of claim 1 , wherein the scheduling engine is further configured to set the UPWC to the sum after performing a plurality of bitwise right shift operations on the sum and before the second set of upstream packets is forwarded to the downstream switch.
9. The system of claim 1 , wherein the plurality of bitwise right shift operations has a cardinality of 3, and wherein the predetermined value is 8.
10. The system of claim 1 , wherein the local switch, the downstream switch, and the at least one upstream source are located on a single chip.
11. The system of claim 1 , wherein the at least one upstream source comprises a processor, wherein the downstream switch is associated with a memory, and wherein at least one of the first set of upstream packets comprises a request from the processor for a data item in the memory.
12. The system of claim 1 , wherein the at least one upstream source comprises a memory, wherein the downstream switch is associated with a processor, and wherein at least one of the first set of upstream packets comprises a data item from the memory for the processor.
13. The system of claim 1 , further comprising:
an aggregate upstream packet counter (AUPC) for storing the sum, wherein the scheduling engine is further configured to set the AUPC to zero before the second set of upstream packets is forwarded.