Single die output power stage using trench-gate low-side and LDMOS high-side MOSFETS, structure and method

1. A method for forming a semiconductor device, the method comprising:

forming, on a semiconductor die, a high-side transistor comprising a lateral diffusion metal oxide semiconductor (LDMOS) device;

forming, on the semiconductor die, a low-side transistor comprising a trench-gate vertical diffusion metal oxide semiconductor (VDMOS) device;

forming, on the semiconductor die, a portion of a gate of the high-side transistor and a portion of a gate of the low-side transistor from a single conductive structure; and

forming a high-side body region and a low-side body region via an unmasked blanket body implant performed in both a layer of the high-side transistor and a layer of the low-side transistor.

2. The method of claim 1 wherein the single conductive structure is a first single conductive structure and the method further comprises:

etching a layer comprising a conductor to form a contact to the semiconductor wafer section, a shield for the portion of the gate of the high-side transistor, a contact to a floating guard ring to the trench-gate VDMOS transistor, and a contact to a source of the trench-gate VDMOS transistor from a second single conductive structure.

3. The method of claim 2 , further comprising etching a layer comprising a conductor to form a drain contact to a drain of the high-side LDMOS transistor, a source contact to a source of the trench-gate low-side VDMOS transistor, a gate contact to the gate of the trench-gate low-side VDMOS device, and a gate contact to the gate of the high-side transistor from a third single conductive structure.

4. The method of claim 1 , further comprising forming a conductive trench-source-contact structure which electrically shorts a gate shield for the high-side LDMOS transistor gate to the substrate, which contacts the semiconductor substrate, and which contacts a body contact on all sides of a portion of the trench-source-contact structure.

5. The method of claim 1 wherein the single conductive structure is a first single conductive structure and the method further comprises forming a second single conductive structure which forms:

a contact to a source region of the high-side transistor;

a contact to a body region of the high-side transistor;

a contact to a source region of the low-side transistor;

a contact to a body region of the low-side transistor;

a gate shield for a transistor gate of the high-side transistor;

an electrical connection between the source and body of the high-side device; and

an electrical connection between a drain of the low-side device and a semiconductor substrate of the semiconductor die.

6. The method of claim 1 , wherein the semiconductor die is a first semiconductor die and the method further comprises:

providing a second semiconductor die different from the first semiconductor die comprising voltage converter controller circuitry; and

electrically coupling the voltage converter controller circuitry with the first semiconductor die.

7. The method of claim 6 , further comprising co-packaging the first semiconductor die and the second semiconductor die into a single semiconductor device.

8. The method of claim 1 wherein the single conductive structure is a first single conductive structure and the method further comprises:

forming a conductive trench contact having at least a portion within a trench in a semiconductor substrate;

forming at least one conductive gate portion of the LDMOS device; and

forming a gate shield interposed between the at least one conductive gate portion of the LDMOS device and a structure which overlies the gate shield,

wherein the gate shield and the conductive trench contact are formed from a second single conductive structure.

9. The method of claim 8 further comprising etching a layer comprising a conductor to define:

a conductive drain interconnect electrically coupled to a drain of the LDMOS device; and

a conductive source interconnect electrically coupled to a source of the VDMOS device,

wherein the conductive drain interconnect and the conductive source interconnect are formed from a third single conductive structure.

10. The method of claim 9 , further comprising:

electrically coupling a portion of the third single conductive structure which forms the conductive drain interconnect to voltage in (VIN); and

electrically coupling a portion of the third single conductive structure which forms the conductive source interconnect to ground.

11. The method of claim 1 further comprising forming a conductive contact within a trench to electrically couple a high-side transistor source and a high-side transistor body.

12. A method of forming a semiconductor device, the method comprising:

forming a high-side transistor comprising a lateral diffusion metal oxide semiconductor (LDMOS) device on a single semiconductor die;

forming a low-side transistor comprising a trench-gate vertical diffusion metal oxide semiconductor (VDMOS) device on the single semiconductor die; and

forming a portion of a gate of the high-side transistor and a portion of a gate of the low-side transistor from a single conductive structure;

wherein forming the high-side transistor comprises:

forming a body region;

forming a body contact region in the body region; and

forming a trench-substrate-contact (TSC) through the body contact region and the body region such that the TSC contacts a top surface of the body contact region and a side of the body contact region.

13. The method of claim 12 wherein the single conductive structure is a first single conductive structure and the method further comprises:

forming a second single conductive structure which forms a contact to the semiconductor wafer section, a shield for the portion of the gate of the high-side transistor, a contact to a floating guard ring to the trench-gate VDMOS transistor, and a contact to a source of the trench-gate VDMOS transistor.

14. The method of claim 13 , further comprising:

forming a third single conductive structure which forms a drain contact to a drain of the high-side LDMOS transistor, a source contact to a source of the trench-gate low-side VDMOS transistor, and a gate contact to the trench-gate low-side VDMOS device gate.

15. The method of claim 12 , wherein forming the TSC comprises forming the TSC such that the TSC electrically shorts a gate shield for the high-side transistor to the substrate, the TSC contacting the semiconductor substrate and the body contact region on all sides of a portion of the TSC.

16. The method of claim 12 , wherein the single semiconductor die is a first semiconductor die and the method further comprising:

forming a second semiconductor die different from the first semiconductor die comprising voltage converter controller circuitry electrically coupled with the first semiconductor die.

17. The method of claim 16 , further comprising co-packaging the first semiconductor die and the second semiconductor die into a single semiconductor device.

18. The method of claim 12 wherein the single conductive structure is a first single conductive structure, and the method further comprises:

forming a conductive trench contact having at least a portion within a trench within a semiconductor substrate;

forming at least one conductive gate portion of the LDMOS device; and

forming a gate shield interposed between the at least one conductive gate portion of the LDMOS device and a structure which overlies the gate shield,

wherein the gate shield and the conductive trench contact are a second single conductive structure.

19. The method of claim 18 further comprising:

forming a conductive drain interconnect electrically coupled to a drain of the LDMOS device; and

forming a conductive source interconnect electrically coupled to a source of the VDMOS device,

wherein the conductive drain interconnect and the conductive source interconnect are a third single conductive structure.

20. The method of claim 19 , further comprising:

electrically coupling the conductive drain interconnect to voltage in (VIN); and

electrically coupling the conductive source interconnect to ground.