Semiconductor memory system
View Patent ↗According to one embodiment, a semiconductor memory system includes a substrate, a plurality of elements and an adhesive portion. The substrate has a multilayer structure in which wiring patterns are formed, and has a substantially rectangle shape in a planar view. The elements are provided and arranged along the long-side direction of a surface layer side of the substrate. The adhesive portion is filled in a gap between the elements and in a gap between the elements and the substrate, where surfaces of the elements are exposed.
1. A semiconductor device comprising:
a substrate; and
a plurality of nonvolatile semiconductor memories mounted on the substrate, wherein the substrate includes:
a first wiring layer in which a first wiring pattern is formed, the first wiring pattern structure to mount the nonvolatile semiconductor memories on a surface layer side of the substrate;
a second wiring layer in which a second wiring pattern is formed on a rear surface layer side of the substrate;
a plurality of third wiring layers formed as an inner layer; and
an insulating layer provided between the first wiring layer and the second wiring layer, and between the second wiring layer and the third wiring layers, wherein
a wiring density of the entire third wiring layers and the second wiring layer that are formed on a rear surface layer side with respect to a center line of a layer structure of the substrate, is equal to or greater than a wiring density of the entire third wiring layers and the first wiring layer that are formed on a surface layer side with respect to the center line of the layer structure of the substrate, a difference between the wiring density of the entire third wiring layers and the second wiring layer and the wiring density of the entire third wiring layers and the first wiring layer being 7.5% or less, and
at least one of the third wiring layers is a shield layer configured to prevent leakage of noise.
2. The semiconductor device according to claim 1 , wherein the shield layer faces the first wiring layer, with the insulating layer provided therebetween.
3. The semiconductor device according to claim 1 , wherein the shield layer faces the second wiring layer, with the insulating layer provided therebetween.
4. The semiconductor device according to claim 2 , wherein a wiring density of the shield layer is 80% or greater.
5. The semiconductor device according to claim 3 , wherein a wiring density of the shield layer is 80% or greater.
6. The semiconductor device according to claim 1 , wherein a surface of the first wiring layer is covered by a solder resist.
7. The semiconductor device according to claim 1 , wherein a surface of the second wiring layer is covered by a solder resist.
8. The semiconductor device according to claim 1 , wherein the nonvolatile semiconductor memories comprise NAND-type flash memories.
9. The semiconductor device according to claim 8 , wherein four NAND-type flash memories are mounted on the first wiring layer side of the substrate.
10. The semiconductor device according to claim 1 , wherein the substrate has a substantially rectangle shape in a plan view.