IP Library Granted Patent US 8,830,773
Granted Patent B2
US 8,830,773 · App. 13/419,293 · Granted Sep 9, 2014

Semiconductor device having compensation capacitance

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Quick Facts
Patent No.
US 8,830,773
App. No.
13/419,293
Granted
Sep 9, 2014
Kind
B2
Abstract

Disclosed herein is a device that includes: first and second memory mats each including a plurality of bit lines; a sense area arranged between the first and second memory mats; a column selection line provided on the first memory mat; and a compensation capacitance provided on the second memory mat. The sense area includes a plurality of sense amplifiers. Each of the sense amplifiers is connected to an associated one or ones of the bit lines. At least one of the sense amplifiers is selected based on a column selection signal supplied via the column selection line. At least a part of the compensation capacitance is formed in a same wiring layer as the column selection line.

Claims (36)

1. A semiconductor device comprising:

a plurality of memory mats arranged in a first direction;

a plurality of sense areas each arranged between two of the memory mats, each of the sense areas including a plurality of sense amplifiers selected based on a column selection signal;

a column decoder generating the column selection signal;

a column selection line extending in the first direction on the memory mats and supplying the column selection signal from the column decoder to the sense areas; and

a compensation capacitance provided on one of the memory mats which is located farther than the other of the memory mats from the column decoder,

wherein the compensation capacitance includes a first capacitance electrode to which a first power source potential is supplied and a second capacitance electrode to which a second power source potential is supplied, and at least one of the first and second capacitance electrodes is formed in a same wiring layer as the column selection line.

2. The semiconductor device as claimed in claim 1 , wherein both the first and second capacitance electrodes are formed in a same wiring layer as the column selection line.

3. The semiconductor device as claimed in claim 1 , wherein

one of the first and second capacitance electrodes is formed in a same wiring layer as the column selection line, and

the other one of the first and second capacitance electrodes is formed in a wiring layer different from the column selection line.

4. The semiconductor device as claimed in claim 1 , wherein the first power source potential is an operating potential of the sense amplifiers.

5. The semiconductor device as claimed in claim 1 , further comprising:

a power source circuit generating the first power source potential; and

a power source line connected between the power source circuit and the first capacitance electrode,

wherein the power source line is formed in a wiring layer different from the column selection line.

6. The semiconductor device as claimed in claim 5 , wherein the power source line is arranged on the memory mats to extend in the first direction.

7. A semiconductor device comprising:

first and second memory mats each including a plurality of bit lines;

a sense area arranged between the first and second memory mats;

a column selection line provided on the first memory mat; and

a compensation capacitance provided on the second memory mat, wherein

the sense area includes a plurality of sense amplifiers,

each of the sense amplifiers is connected to an associated one or ones of the bit lines,

at least one of the sense amplifiers is selected based on a column selection signal supplied via the column selection line, and

at least a part of the compensation capacitance is formed in a same wiring layer as the column selection line.

8. The semiconductor device as claimed in claim 7 , wherein the column selection line is not provided on the second memory mat.

9. The semiconductor device as claimed in claim 7 , wherein each of the sense amplifiers is connected to an associated one of the bit lines provided on the first memory mat and connected to an associated one of the bit line provided on the second memory mat.

10. The semiconductor device as claimed in claim 7 , wherein

the compensation capacitance includes a first capacitance electrode to which a first power source potential is supplied and a second capacitance electrode to which a second power source potential is supplied, and

both the first and second capacitance electrodes are formed in a same wiring layer as the column selection line.

11. The semiconductor device as claimed in claim 10 , wherein the first power source potential is an operating potential of the sense amplifiers.

12. The semiconductor device as claimed in claim 10 , further comprising:

a power source circuit generating the first power source potential; and

a power source line connected between the power source circuit and the first capacitance electrode,

wherein the power source line is formed in a wiring layer different from the column selection line.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 15, 2014
From: ELPIDA MEMORY, INC.
To: PS4 LUXCO S.A.R.L.
Reel/Frame 032898/0465 →
SECURITY AGREEMENT Recorded Jul 29, 2013
From: PS4 LUXCO S.A.R.L.
To: ELPIDA MEMORY INC.
Reel/Frame 032414/0261 →