IP Library Granted Patent US 8,871,570
Granted Patent B2
US 8,871,570 · App. 13/419,447 · Granted Oct 28, 2014

Method of fabricating integrated optoelectronic interconnects with side mounted transducer

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,871,570
App. No.
13/419,447
Granted
Oct 28, 2014
Kind
B2
Abstract

A method for fabricating an optical interconnect includes producing a semiconductor wafer that includes multiple first dies. Each first die includes circuitry disposed over a surface of the wafer and connected to conductive vias arranged in rows. The multiple first dies are diced by cutting the wafer across the rows of the vias, such that, in each first die, the cut vias form respective contact pads on a side face of the first die that is perpendicular to the surface. A second semiconductor die including one or more optoelectronic transducers is attached to the contact pads, so as to connect the transducers to the circuitry.

Claims (17)

1. A method for fabricating an optical interconnect, the method comprising:

producing a semiconductor wafer comprising multiple first dies, each first die comprising circuitry disposed over a surface of the wafer and connected to conductive vias arranged in rows;

dicing the multiple first dies by cutting the wafer across the rows of the vias, such that, in each first die, the cut vias form respective contact pads on a side face of the first die that is perpendicular to the surface; and

attaching to the contact pads a second semiconductor die comprising one or more optoelectronic transducers, so as to connect the transducers to the circuitry.

2. The method according to claim 1 , wherein producing the wafer comprises forming the conductive vias in side-contact rings that surround the first dies, and wherein dicing the first dies comprises exposing cross-sections of the vias along the side face of each first die.

3. The method according to claim 1 , and comprising disposing a gold metal layer over the contact pads.

4. The method according to claim 1 , wherein the conductive vias comprise gold-filled through-silicon vias (TSV).

5. The method according to claim 1 , wherein attaching the second semiconductor die comprises disposing ball bumps onto the contact pads and melting the ball bumps.

6. The method according to claim 1 , and comprising forming integrated respective lenses opposite the optoelectronic transducers.

7. An apparatus, comprising:

a first semiconductor die, which comprises circuitry connected to conductive vias arranged in rows disposed over a surface of a semiconductor wafer and is cut from the wafer across a row of the vias such that the cut vias form respective contact pads on a side face of the first die that is perpendicular to a surface of the first die; and

a second semiconductor die, which comprises one or more optoelectronic transducers and is attached onto the contact pads so as to connect the transducers to the circuitry.

8. The apparatus according to claim 7 , wherein the conductive vias are located in a side-contact ring, which surrounds the first die before the first die is cut from the wafer, such that cross-sections of the vias are exposed along the side face of the first die when the first die is cut from the wafer.

9. The apparatus according to claim 7 , and comprising a gold metal layer that is disposed over the contact pads.

10. The apparatus according to claim 7 , wherein the conductive vias comprise gold-filled through-silicon vias (TSV).

11. The apparatus according to claim 7 , wherein the second semiconductor die is attached to the first die using ball bumps that are placed onto the contact pads and melted.

12. The apparatus according to claim 7 , and comprising respective integrated lenses that are formed opposite the optoelectronic transducers.

Assignments (2)
RELEASE OF SECURITY INTEREST IN PATENT COLLATERAL AT REEL/FRAME NO. 37900/0720 Recorded Jul 13, 2018
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MELLANOX TECHNOLOGIES, LTD.
Reel/Frame 046542/0792 →
PATENT SECURITY AGREEMENT Recorded Feb 24, 2016
From: MELLANOX TECHNOLOGIES, LTD.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 037900/0720 →