Non-volatile memory and method with host controlled caching
View Patent ↗A flash memory device includes a storage area having a main memory portion and a cache memory portion storing at least one bit per cell less than the main memory portion; and a controller that manages data transfer between the cache memory portion and the main memory portion according to at least one caching command received from a host. The management of data transfer, by the controller, includes transferring new data from the host to the cache memory portion, copying the data from the cache memory portion to the main memory portion and controlling (enabling/disabling) the scheduling of cache cleaning operations.
1. A flash memory device comprising:
(a) a storage area including:
(i) a main memory portion; and
(ii) a cache memory portion, where said cache memory portion is operative to store at least one bit per cell less than said main memory portion; and
(b) a controller operative to manage data transfer between said cache memory portion and said main memory portion according to at least one caching command received from a host, and
wherein said at least one caching command includes a command to return to the host a status of the cache memory.
2. The flash memory device of claim 1 , wherein said status includes indications of the cache memory being completely empty.
3. The flash memory device of claim 1 , wherein said status includes indications of the cache memory being completely full.
4. The flash memory device of claim 1 , wherein said status includes indications of the cache memory being partially full.
5. The flash memory device of claim 1 , wherein said status includes a numerical measurement of the relative fullness of the cache memory.
6. The flash memory device of any one of claims 1 - 5 , wherein said main memory portion and said cache memory portion are fixed portions of said storage area.
7. The flash memory device of any one of claims 1 - 5 , wherein said main memory portion and said cache memory portion are allocated using a mixed cache method.
8. A method of managing operation of a flash memory device that includes a storage area having a main memory portion and a cache memory portion operative to store at least one bit per cell less than the main memory portion, the method comprising the steps of:
(a) receiving data from a host;
(b) storing said received data in the cache memory portion; and
(c) according to at least one caching command received from said host, managing data transfer between the cache memory portion and the main memory portion; and
wherein said at least one caching command includes a command to return to the host a status of the cache memory.
9. The method of claim 8 , wherein said status includes indications of the cache memory being completely empty.
10. The method of claim 8 , wherein said status includes indications of the cache memory being completely full.
11. The method of claim 8 , wherein said status includes indications of the cache memory being partially full.
12. The method of claim 8 , wherein said status includes a numerical measurement of the relative fullness of the cache memory.
13. The method of any one of claims 8 - 12 , wherein said main memory portion and said cache memory portion are fixed portions of said storage area.
14. The method of any one of claims 8 - 12 , wherein said main memory portion and said cache memory portion are allocated using a mixed cache method.