IP Library Granted Patent US 8,889,446
Granted Patent B2
US 8,889,446 · App. 13/419,855 · Granted Nov 18, 2014

Polysilicon thin film transistor device and method of fabricating the same

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Quick Facts
Patent No.
US 8,889,446
App. No.
13/419,855
Granted
Nov 18, 2014
Kind
B2
Abstract

A polysilicon thin film transistor device includes a gate metal pattern including a gate electrode and a gate line formed on a substrate, the gate metal pattern having a stepped portion, a gate insulating film formed on the gate metal pattern, a polysilicon semiconductor layer formed on the gate insulating film, the polysilicon semiconductor layer including an active region, lightly doped drain regions, a source region, and a drain region, a source electrode connected to the source region and a drain electrode connected to the drain region on the polysilicon semiconductor layer, and a pixel electrode connected with the drain electrode.

Claims (30)

1. A method of fabricating a polysilicon thin film transistor device, comprising:

forming a gate metal pattern made of a single layer of a singular metal material having a stepped portion formed on a substrate, wherein either side of the stepped portion of the gate metal pattern has a different thickness;

forming a gate insulating film on the gate metal pattern;

forming a polysilicon semiconductor layer on the gate insulating film;

forming an active region, lightly doped drain regions, a source region and a drain region on the polysilicon semiconductor layer by implanting an impurities;

forming a source electrode electrically connected to the source region and forming a drain electrode electrically connected to the drain region; and

forming a pixel electrode connected to the drain electrode,

wherein the gate metal pattern comprises a gate electrode and a gate line,

wherein the gate electrode and the gate line are formed of the same singular metal material in the same single layer, and

wherein the gate electrode has a thickness less than a thickness of the gate line.

2. The method according to claim 1 , further comprising forming an interlayer insulating layer having a contact hole for connecting the source region to the source electrode for connecting the drain region to the drain electrode, after the forming a polysilicon semiconductor layer.

3. The method according to claim 1 , wherein the forming the gate metal pattern comprises:

depositing the single layer of the singular gate metal material on the substrate;

coating a photoresist film on the gate metal material;

forming a photoresist film pattern having a stepped portion by diffraction-exposing the coated photoresist film;

patterning the gate electrode and the gate line by a first etching of the gate metal material;

performing a second etching of the gate electrode by etching the photoresist film pattern; and

removing the photoresist film pattern.

4. The method according to claim 3 , further comprising removing the photoresist film pattern disposed on the gate electrode by ash-treating the photoresist pattern having the stepped portion, after the patterning the gate electrode and the gate line.

5. A method of fabricating a polysilicon thin film transistor device, comprising:

forming a gate metal on a substrate;

forming a photoresist film pattern having a stepped portion by coating a photoresist film on the gate metal and diffraction-exposing the coated photoresist film;

patterning a gate electrode and a gate line by a first etching of the gate metal exposed by the photoresist film pattern;

performing a second etching of the gate electrode such that the gate electrode and the gate line have a thickness difference;

forming a gate insulating film on the patterned gate metal;

forming a polysilicon layer on the gate insulating film;

forming a source electrode electrically connected to a source region of the polysilicon layer and forming a drain electrode electrically connected to a drain region on the polysilicon layer; and

forming a pixel electrode connected to the drain electrode,

wherein the patterned gate metal is formed of a singular metal composition in a single layer, the gate electrode having a thickness less than a thickness of the gate line.

6. The method according to claim 5 , further comprising, removing the photoresist film pattern disposed on the gate electrode by ash-treating the photoresist pattern having the stepped portion, after the patterning the gate electrode and the gate line.