Semiconductor DRAM with non-linear word line discharge

1. A semiconductor device comprising:

first and second memory cell arrays arranged side by side in a first direction, each of said first and said second memory cell arrays comprising a memory cell mat that includes a word line and a bit line, a sub-word driver circuit that drives said word line, and a first control unit that controls said sub-word driver circuit; and

a first region that is disposed between said first memory cell array and said second memory cell array, and that includes a second control unit that controls said sub-word driver circuit;

wherein said first control unit has a first circuit unit;

said second control unit includes a third circuit unit that operates at a first power supply voltage having a first power supply potential as a low potential side and a fourth circuit unit that operates at a second power supply voltage having a second power supply potential lower than said first power supply potential as a low potential side, supplies a first control signal to said sub-word driver circuit, and supplies a second control signal to said first circuit unit of said first control unit;

said first circuit unit of said first control unit operates at a third power supply voltage having said second power supply potential as a low potential side without receiving said first power supply potential, receives said second control signal, and supplies a third control signal to said sub-word driver circuit; and

said sub-word driver circuit receives said first control signal and said third control signal, and nonlinearly deactivates said word line of an active state.

2. The semiconductor device according to claim 1 , wherein said sub-word driver circuit decreases a speed of deactivating said word line while said word line is being put into an inactive state.

3. The semiconductor device according to claim 2 , wherein equalization of said bit line is started after the speed of deactivating said word line has changed.

4. The semiconductor device according to claim 1 , wherein said first circuit unit of said first control unit changes a potential of said third control signal in an active state of said word line; said second control unit changes a potential of said first control signal in an active state of said word line; and said sub-word driver circuit starts the deactivation of said word line of an active state when at least one of potentials of said first control signal and said third control signal changes.

5. The semiconductor device according to claim 1 , wherein

said first control unit further has a second circuit unit that operates at said second power supply voltage;

said second control unit further supplies a fourth control signal to said second circuit unit of said first control unit;

said second circuit unit of said first control unit receives said fourth control signal and supplies a fifth control signal to said sub-word driver circuit; and

said sub-word driver circuit receives said first control signal, said third control signal and said fifth control signal, and nonlinearly deactivates said word line of an active state.

6. The semiconductor device according to claim 1 , wherein

said first control unit further has a second circuit unit that operates at said third power supply voltage;

said second control unit further supplies a fourth control signal to said second circuit unit of said first control unit;

said second circuit unit of said first control unit receives said fourth control signal and supplies a fifth control signal to said sub-word driver circuit; and

said sub-word driver circuit receives said first control signal, said third control signal and said fifth control signal, and nonlinearly deactivates said word line of an active state.

7. The semiconductor device according to claim 1 , wherein said sub-word driver circuit has a plurality of transistors used to deactivate said word line, and changes a speed of deactivating said word line by changing the number of said transistors used to deactivate said word line.

8. A device comprising:

a memory cell array including a plurality of word lines, a plurality of bit lines each intersecting the word lines and a plurality of memory cells each disposed at an associated one of intersections of the word and bit lines, each of the memory cells including a capacitor and a cell transistor connected in series between an associated one of the bit lines and a plate potential line, the cell transistor including a gate connected to an associated one of the word line;

a driver circuit including a plurality of driver units each provided for an associated one of the word lines, each of the driver units including a first transistor connected between a first circuit node and the associated one of the word lines, and a second transistor connected between the associated one of the word lines and a second node, and a third transistor connected in parallel to the second transistor, the second and third transistors being rendered conductive to drive the associated one of the word lines from a selection level to an intermediate level at a first rate, and one of the second and third transistors being rendered nonconductive to drive the associated one of the word lines from the intermediate level to a non-selection level at a second rate; and

a control circuit configured to control each of the driver units to drive the associated one of the word lines from the selection level to the intermediate level at the first rate and from the intermediated level to the non-selection level at the second rate, the intermediate level being between the selection and non-selection levels, and the first rate being greater than the second rate.