Enhanced efficiency low-dropout linear regulator and corresponding method
View Patent ↗A low-dropout linear regulator includes an error amplifier which includes a cascaded arrangement of a differential amplifier and a gain stage. The gain stage includes a transistor driven by the differential amplifier to produce at a drive signal for an output stage of the regulator. The transistor is interposed over its source-drain line between a first resistive load included in a RC network creating a zero in the open loop gain of the regulator, and a second resistive load to produce a drive signal for the output stage of the regulator. The second resistive load is a non-linear compensation element to render current consumption linearly proportional to the load current to the regulator. The first resistive load is a non-linear element causing the frequency of said zero created by the RC network to decrease as the load current of the regulator decreases.
1. A low-dropout regulator comprising:
a differential amplifier having an input configured to receive a reference voltage;
a level shifter having an input coupled to an output of the differential amplifier;
an intermediate stage having an input coupled to an output of the level shifter;
an output stage having an input coupled to an output of the intermediate stage; and
a voltage divider coupled to an output of the output stage and to the differential amplifier;
said intermediate stage comprising
a first transistor having a gate terminal coupled to the output of the level shifter,
a second transistor coupled between a supply voltage and the first transistor and having a gate terminal coupled to the input of the output stage, and
a third transistor coupled between the first transistor and a reference voltage.
2. The low-dropout regulator of claim 1 wherein the differential amplifier comprises an adaptive bias current source.
3. The low-dropout regulator of claim 1 wherein the differential amplifier comprises an input configured to receive a bias voltage.
4. The low-dropout regulator of claim 1 wherein the level shifter comprises:
a first transistor configured to receive a bias voltage; and
a second transistor having a gate terminal configured to define the input of the level shifter and a source terminal configured to define the output of the level shifter.
5. The low-dropout regulator of claim 1 wherein the second transistor comprises a diode-connected transistor.
6. The low-dropout regulator of claim 1 further comprising a capacitor coupled between a source terminal of the third transistor and the reference voltage.
7. The low-dropout regulator of claim 1 wherein the output stage comprises a power transistor.
8. The low-dropout regulator of claim 1 further comprising a resistive load coupled to the output of the output stage.
9. The low-dropout regulator of claim 1 further comprising a capacitive load coupled to the output of the output stage.
10. A low-dropout regulator comprising:
a differential amplifier having an input configured to receive a reference voltage;
a level shifter having an input coupled to an output of the differential amplifier;
a first intermediate stage having an input coupled to an output of the level shifter;
a second intermediate stage having an input coupled to the output of the level shifter;
a first output stage having an input coupled to an output of the first intermediate stage;
a second output stage having an input coupled to an output of the second intermediate stage; and
a voltage divider coupled to a combined output of the first output stage and the second output stage, and to the differential amplifier;
the first and second intermediate stages each comprising
a first transistor,
a second transistor coupled to the first transistor,
a first current mirror coupled to the second transistor, and
a second current mirror coupled to the first current mirror.
11. The low-dropout regulator of claim 10 wherein the differential amplifier comprises an adaptive bias current source.
12. The low-dropout regulator of claim 10 wherein the differential amplifier comprises an input configured to receive a bias voltage.
13. The low-dropout regulator of claim 10 wherein the level shifter comprises;
a first transistor configured to receive a bias voltage; and
a second transistor having a gate terminal configured to define the input of the level shifter and a source terminal configured to define the output of the level shifter.
14. The low-dropout regulator of claim 10 wherein the first and second intermediate stages each comprises a capacitor.
15. The low-dropout regulator of claim 10 wherein the first and second intermediate stages are interconnected through respective internal nodes thereof.
16. The low-dropout regulator of claim 10 wherein the first and second output stages each comprises a transistor.
17. The low-dropout regulator of claim 10 further comprising a resistive load coupled to the combined output of the first output stage and the second output stage.
18. The low-dropout regulator of claim 10 further comprising a capacitive load coupled to the combined output of the first output stage and the second output stage.