Systems and methods involving control-I/O buffer enable circuits and/or features of saving power in standby mode
Implementations herein involve control I/O buffer enable circuitry and/or features of saving power in standby mode. In illustrative embodiments, aspects of the present innovations may be directed to providing low standby power consumption, such as providing low standby power consumption in high-speed synchronous SRAM and RLDRAM devices.
1. A semiconductor device comprising:
an array of memory cells;
a control-peripheral circuit including an internal-peripheral circuit coupled to the array of memory cells;
an i/o-peripheral circuit coupled to the array of memory cells; and
a clock frequency detected control-i/o buffer enable circuit coupled to the i/o-peripheral circuit;
wherein the clock frequency detected control-i/o buffer enable circuit includes a clock frequency detector and a control-i/o buffer enable circuit; and
wherein a first reference signal provided to the clock frequency detector is associated with a band gap reference circuit.
2. The device of claim 1 :
wherein the clock frequency detector has a frequency detector receiving a clock signal from external clock pad signal associated with the control-peripheral circuit and a first reference signal, and then generating first output set signals at the clock frequency detector;
wherein a first one of the first output set signals is coupled to a control-i/o buffer enable or a second one of the first output set signals is coupled to the internal-peripheral circuit; and
wherein the control-i/o buffer enable circuit receives a control set signal and the first one of the first output set signals, and then produces second output set signals at the control-i/o buffer enable circuit; and
wherein the second output set signals from first to nth are selectively coupled to the control-peripheral circuit, the i/o-peripheral circuit, or the internal-peripheral circuit.
3. The device of claim 2 , wherein a control set signal received by the control-i/o buffer enable circuit comprises a power-up up signal, an external sourced reference voltage signal, a bscan related signal, and/or a write cycle related signal.
4. The device of claim 1 , wherein the control-peripheral circuitry includes an zq generator.
5. The device of claim 4 , wherein a control set signal received by the control-i/o buffer enable circuit comprises a power-up up signal, an external sourced reference voltage signal, a bscan related signal, and/or a write cycle related signal.
6. The device of claim 5 , wherein some one or more input buffers of the semiconductor device are maintained in an on state after power up is complete.
7. The device of claim 6 wherein the one or more input buffers include a small clock input buffer, a TMS buffer, and a TCK buffer.
8. The device of claim 1 , wherein a control set signal received by the control-i/o buffer enable circuit comprises a power-up up signal, an external sourced reference voltage signal, a bscan related signal, and/or a write cycle related signal.
9. The device of claim 8 , wherein one or more input buffers of the semiconductor device are maintained in an on state after power up is complete.
10. The device of claim 9 wherein the one or more input buffers include a small clock input buffer, a TMS buffer, and a TCK buffer.
11. The device of claim 1 , wherein one or more first output set signals are synchronized with a falling edge of a next external clock signal whenever updating, wherein the next external clock signal is characterized in that, at cycle N, an external clock frequency is sensed, and then output as a detected frequency at a next falling edge of cycle N+1.
12. The device of claim 1 , wherein one or more input buffers of the semiconductor device are maintained in an on state after power up is complete.
13. The device of claim 12 wherein the one or more input buffers include a small clock input buffer, a TMS buffer, and a TCK buffer.
14. The device of claim 1 wherein one or more first output set signals are synchronized with a falling edge of a next external clock signal whenever updating, wherein the next external clock signal is characterized in that, at cycle N, an external clock frequency is sensed, and then output as a detected frequency at a next falling edge of cycle N+1.
15. The device of claim 14 wherein the clock frequency is sensed or latched at a rising edge of cycle N, output to a next flip-flop at a falling edge of the cycle N, and then provided as the detected frequency output at a next falling edge of cycle N+1.
16. The device of claim 14 wherein the clock frequency is sensed and latched at a rising edge of cycle N, output to a next flip-flop at a falling edge of the cycle N, and then provided as the detected frequency output at a next falling edge of cycle N+1.
17. A semiconductor device comprising:
an array of memory cells;
a control-peripheral circuit including an internal-peripheral circuit coupled to the array of memory cells;
an i/o-peripheral circuit coupled to the array of memory cells; and
a clock frequency detected control-i/o buffer enable circuit coupled to the i/o-peripheral circuit;
wherein the clock frequency detected control-i/o buffer enable circuit includes a clock frequency detector and a control-i/o buffer enable circuit; and
wherein one or more first output set signals are synchronized with a falling edge of a next external clock signal whenever updating, wherein the next external clock signal is characterized in that, at cycle N, an external clock frequency is sensed, and then output as a detected frequency at a next falling edge of cycle N+1.
18. The device of claim 17 :
wherein the clock frequency detector has a frequency detector receiving a clock signal from external clock pad signal associated with the control-peripheral circuit and a first reference signal, and then generating first output set signals at the clock frequency detector;
wherein a first one of the first output set signals is coupled to a control-i/o buffer enable or a second one of the first output set signals is coupled to the internal-peripheral circuit;
wherein the control-i/o buffer enable circuit receives a control set signal and the first one of the first output set signals, and then produces second output set signals at the control-i/o buffer enable circuit; and
wherein the second output set signals from first to nth are selectively coupled to the control-peripheral circuit, the i/o-peripheral circuit, or the internal-peripheral circuit.
19. The device of claim 17 , wherein the control-peripheral circuit includes an zq generator.
20. The device of claim 17 , wherein a control set signal received by the control-i/o buffer enable circuit comprises a power-up up signal, an external sourced reference voltage signal, a bscan related signal, and/or a write cycle related signal.
21. The device of claim 17 , wherein one or more input buffers of the semiconductor device are maintained in an on state after power up is complete.
22. The device of claim 21 wherein the one or more input buffers include a small clock input buffer, a TMS buffer, and a TCK buffer.
23. The device of claim 17 wherein the clock frequency is sensed or latched at a rising edge of cycle N, output to a next flip-flop at a falling edge of the cycle N, and then provided as the detected frequency output at a next falling edge of cycle N+1.
24. The device of claim 17 wherein the clock frequency is sensed and latched at a rising edge of cycle N, output to a next flip-flop at a falling edge of the cycle N, and then provided as the detected frequency output at a next falling edge of cycle N+1.
25. A semiconductor device comprising:
an array of memory cells;
a control-peripheral circuit including an internal-peripheral circuit coupled to the array of memory cells;
an i/o-peripheral circuit coupled to the array of memory cells; and
a clock frequency detected control-i/o buffer enable circuit coupled to the i/o-peripheral circuit;
wherein the clock frequency detected control-i/o buffer enable circuit includes a clock frequency detector and a control-i/o buffer enable circuit;
wherein a control set signal received by the control-i/o buffer enable circuit comprises a power-up up signal, an external sourced reference voltage signal, a bscan related signal, and/or a write cycle related signal; and
wherein one or more first output set signals are synchronized with a falling edge of a next external clock signal whenever updating, wherein the next external clock signal is characterized in that, at cycle N, an external clock frequency is sensed, and then output as a detected frequency at a next falling edge of cycle N+1.
26. The device of claim 25 :
wherein the clock frequency detector has a frequency detector receiving a clock signal from external clock pad signal associated with the control-peripheral circuit and a first reference signal, and then generating first output set signals at the clock frequency detector;
wherein a first one of the first output set signals is coupled to a control-i/o buffer enable or a second one of the first output set signals is coupled to the internal-peripheral circuit;
wherein the control-i/o buffer enable circuit receives a control set signal and the first one of the first output set signals, and then produces second output set signals at the control-i/o buffer enable circuit; and
wherein the second output set signals from first to nth are selectively coupled to the control-peripheral circuit, the i/o-peripheral circuit, or the internal-peripheral circuit.
27. The device of claim 25 , wherein the control-peripheral circuit includes an zq generator.
28. The device of claim 25 , wherein a control set signal received by the control-i/o buffer enable circuit comprises a power-up up signal, an external sourced reference voltage signal, a bscan related signal, and/or a write cycle related signal.
29. The device of claim 25 , wherein one or more input buffers of the semiconductor device are maintained in an on state after power up is complete.
30. The device of claim 29 wherein the one or more input buffers include a small clock input buffer, a TMS buffer, and a TCK buffer.
31. The device of claim 25 wherein the clock frequency is sensed or latched at a rising edge of cycle N, output to a next flip-flop at a falling edge of the cycle N, and then provided as the detected frequency output at a next falling edge of cycle N+1.
32. The device of claim 25 wherein the clock frequency is sensed and latched at a rising edge of cycle N, output to a next flip-flop at a falling edge of the cycle N, and then provided as the detected frequency output at a next falling edge of cycle N+1.