Voltage regulator with adaptive miller compensation

1. A voltage regulator with adaptive Miller compensation, comprising;

a first amplifier coupled to receive a reference voltage and a feedback voltage;

a second amplifier coupled to receive an output of the first amplifier;

an adaptive compensation circuit with two ends that are coupled to an input node and an output node of the second amplifier respectively, the adaptive compensation circuit comprising a compensation capacitor and a compensation transistor that are serially connected;

a bias circuit configured to generate a proper bias control voltage to dynamically control the adaptive compensation circuit in a manner that the adaptive compensation transistor operates in a deep triode region with weakly-inverted channel or strongly-inverted channel; and

an output circuit coupled to receive the output of the second amplifier, the output circuit being configured to generate an output voltage of the voltage regulator according to which the feedback voltage is generated;

wherein a resistance of the compensation transistor varies according to a load of the voltage regulator under control of the bias control voltage; and

wherein the bias circuit generates a mirror current that copies at least a portion of a current flowing in the output circuit, and the bias control voltage is then generated according to the mirror current.

2. The voltage regulator of claim 1 , wherein the first amplifier comprises a differential amplifier or a folded-cascode amplifier with a non-inverting input node and an inverting input node coupled to the reference voltage and the feedback voltage respectively.

3. The voltage regulator of claim 1 , wherein the second amplifier comprises a common source amplifier.

4. The voltage regulator of claim 3 , wherein the second amplifier comprises a p-type metal-oxide-semiconductor (PMOS) transistor and an n-type metal-oxide-semiconductor (NMOS) transistor that are serially connected by electrically connecting a drain of the PMOS transistor with a drain of the NMOS transistor, wherein a gate of the PMOS transistor or the NMOS transistor is configured as the input node of the second amplifier, and an interconnect node of the PMOS transistor and the NMOS transistor is configured as the output node of the second amplifier.

5. The voltage regulator of claim 1 , wherein the adaptive compensation circuit further comprises a compensation resistor serially connected with the compensation capacitor and the compensation transistor.

6. The voltage regulator of claim 1 , wherein the compensation transistor comprises a metal-oxide-semiconductor (MOS) transistor with a gate coupled to receive the bias control voltage.

7. The voltage regulator of claim 1 , wherein the bias circuit comprises:

a mirror transistor configured to generate the mirror current; and

at least one diode-connected transistor serially connected with the mirror transistor;

wherein an interconnect node between the mirror transistor and the at least one diode-connected transistor provides the bias control voltage.

8. The voltage regulator of claim 7 , wherein the output circuit comprises:

a voltage divider configured to generate the feedback voltage; and

a power transistor serially connected with the voltage divider, wherein a current flowing in the power transistor varies according to the load, and at least a portion of the current flowing in the power transistor is copied in the mirror transistor of the bias circuit.

9. The voltage regulator of claim 7 , wherein the bias control voltage increases when the load increases, and an overdrive voltage of the diode-connected transistor is greater than zero, such that the compensation transistor operates in the deep triode region with strongly-inverted channel; and the bias control voltage decreases when the load decreases, and the overdrive voltage of the diode-connected transistor is less than zero, such that the compensation transistor operates in the deep triode region with weakly-inverted channel.

10. The voltage regulator of claim 9 , wherein the bias circuit further comprises a bias sub-circuit that is independent of the load for providing an internal bias voltage to one of the at least one diode-connected transistor, such that the compensation transistor operates in the deep triode region with weakly-inverted channel in the zero load.

11. The voltage regulator of claim 10 , wherein the bias sub-circuit comprises a MOS transistor with a gate fixedly biased, and a drain electrically connected to a gate of one of the at least one diode-connected transistor.