Nonvolatile semiconductor memory device
View Patent ↗According to one embodiment, a nonvolatile semiconductor memory device includes: a stacked body including a plurality of electrode layers and a plurality of insulating layers, which are alternately stacked, and diffusion suppressing layers each provided between each of the plurality of electrode layers and each of the plurality of insulating layers; and a memory film provided on a side wall of a hole penetrating the stacked body in a stacking direction. Each of the plurality of electrode layers is a first semiconductor layer containing a first impurity element. The diffusion suppressing layer is a second semiconductor layer containing a second impurity element which is different from the first impurity element. The diffusion suppressing layer is a film having an effect of suppressing diffusion of the first impurity element.
1. A nonvolatile semiconductor memory device comprising:
a stacked body including a plurality of electrode layers and a plurality of insulating layers, which are alternately stacked, and diffusion suppressing layers each provided between each of the plurality of electrode layers and each of the plurality of insulating layers;
a memory film provided on a side wall of a hole penetrating the stacked body in a stacking direction; and
a channel body layer provided on the memory film,
each of the plurality of electrode layers being a first semiconductor layer containing a first impurity element,
the diffusion suppressing layer being a second semiconductor layer containing a second impurity element which is different from the first impurity element, and
the diffusion suppressing layer being a film having an effect of suppressing diffusion of the first impurity element.
2. The device according to claim 1 , wherein a concentration of the first impurity element in a depth direction of the first semiconductor layer is relatively higher at the center of the first semiconductor layer between an upper face and a lower face of the first semiconductor layer than at the upper face and the lower face.
3. The device according to claim 1 , wherein each of the plurality of electrode layers is a gate electrode facing the channel body layer via the memory film.
4. The device according to claim 1 , wherein the first impurity element is a group XIII element or a group XV element.
5. The device according to claim 1 , wherein the second impurity element is carbon.
6. The device according to claim 1 , wherein a principal ingredient of the first semiconductor layer and a principal ingredient of the second semiconductor layer are silicon.
7. The device according to claim 1 , wherein the first semiconductor layer and the second semiconductor layer are made of polycrystalline silicon.
8. The device according to claim 1 , wherein the diffusion suppressing layer does not intervene between the memory film provided on the side wall of the hole and the electrode layer.
9. A nonvolatile semiconductor memory device comprising:
a stacked body including a plurality of electrode layers and a plurality of insulating layers, which are alternately stacked, and diffusion suppressing layers each provided between each of the plurality of electrode layers and each of the plurality of insulating layers; and
a memory film provided on a side wall of a hole penetrating the stacked body in a stacking direction,
each of the plurality of electrode layers being a first semiconductor layer containing a first impurity element,
the diffusion suppressing layer being a second semiconductor layer containing a second impurity element which is different from the first impurity element, and
the diffusion suppressing layer being a film having an effect of suppressing diffusion of the first impurity element.
10. The device according to claim 9 , wherein a concentration of the first impurity element in a depth direction of the first semiconductor layer is relatively higher at the center of the first semiconductor layer between an upper face and a lower face of the first semiconductor layer than at the upper face and the lower face.
11. The device according to claim 9 , wherein each of the plurality of electrode layers is a gate electrode facing a channel body layer via the memory film.
12. The device according to claim 9 , wherein the first impurity element is a group XIII element or a group XV element.
13. The device according to claim 9 , wherein the second impurity element is carbon.
14. The device according to claim 9 , wherein a principal ingredient of the first semiconductor layer and a principal ingredient of the second semiconductor layer are silicon.
15. The device according to claim 9 , wherein the first semiconductor layer and the second semiconductor layer are made of polycrystalline silicon.
16. The device according to claim 9 , wherein the diffusion suppressing layer does not intervene between the memory film provided on the side wall of the hole and the electrode layer.