Implementing memory interface with configurable bandwidth
A method and system are provided for implementing enhanced memory performance management with configurable bandwidth versus power usage in a chip stack of memory chips. A chip stack of memory chips is connected in a predefined density to allow a predefined high bandwidth connection between each chip in the stack, such as with through silicon via (TSV) interconnections. Large-bandwidth data transfers are enabled from the memory chip stack by trading off increased power usage for memory performance on a temporary basis.
1. A method for implementing enhanced memory performance management comprising:
providing at least one memory chip stack having a predefined connection density to enable a predefined high bandwidth connection between each chip in said memory chip stack; and
providing said at least one memory chip stack with a memory controller and a plurality of chip rank levels in said memory chip stack including at least a chip rank level one adjacent said controller; a chip rank level two above said chip rank level one; and a chip level three above said chip rank level two;
providing a normal bandwidth configuration for said at least one memory chip stack with said chip rank level one with a first bandwidth for data; said chip rank level two with a second bandwidth for data and said chip rank level three with a third bandwidth for data; said first bandwidth greater than both said second bandwidth and said third bandwidth;
selectively enabling a high bandwidth data transfer from said memory chip stack on a temporary basis; said high bandwidth data transfer including an equal bandwidth for said first bandwidth, said second bandwidth and said third bandwidth.
2. The method as recited in claim 1 wherein providing at least one memory chip stack having a predefined connection density includes connecting said memory chip stack in a predefined density with through silicon via (TSV) interconnections.
3. The method as recited in claim 1 wherein selectively enabling a high bandwidth data transfer from said memory chip stack on a temporary basis includes providing said memory controller coupled to said at least one memory chip stack, said controller using said bandwidth data transfer with said equal bandwidth for said first bandwidth, said second bandwidth and said third bandwidth from said memory chip stack.
4. The method as recited in claim 3 wherein said memory controller selectively enables said high bandwidth data transfer from said memory chip stack on said temporary basis.
5. The method as recited in claim 3 wherein said memory controller selectively requests data at a higher speed than a normal data read speed for the high bandwidth data transfers.
6. The method as recited in claim 1 wherein providing said at least one memory chip stack having a predefined connection density includes providing said at least one memory chip stack of dynamic random access memory (DRAM) chips.
7. The method as recited in claim 1 wherein selectively enabling a high bandwidth data transfer from said memory chip stack on a temporary basis includes receiving a request for a large direct memory access (DMA).
8. The method as recited in claim 1 wherein providing said at least one memory chip stack having a predefined connection density includes providing a silicon carrier including said memory controller and providing said memory chip stack of a plurality of dynamic random access memory (DRAM) chips.
9. The method as recited in claim 8 includes providing said silicon carrier with first level custom DRAM chips and said controller.
10. A system for implementing memory performance management in a computer system comprising:
a memory including at least one memory chip stack having a predefined connection density to enable a predefined high bandwidth connection between each chip in said memory chip stack;
a memory controller coupled to said at least one memory chip stack; and said memory chip stack including a plurality of chip rank levels with a chip rank level one adjacent said controller; a chip rank level two above said chip rank level one; and a chip level three above said chip rank level two;
a data transfer bandwidth control;
said memory controller, responsive to said data transfer bandwidth control, providing a normal bandwidth configuration for said at least one memory chip stack including said chip rank level one with a first bandwidth for data; said chip rank level two with a second bandwidth for data and said chip rank level three with a third bandwidth for data; said first bandwidth greater than both said second bandwidth and said third bandwidth;
said memory controller, responsive to said data transfer bandwidth control, selectively enabling a high bandwidth data transfer from said memory chip stack on a temporary basis; said high bandwidth data transfer including an equal bandwidth for said first bandwidth, said second bandwidth and said third bandwidth.
11. The system as recited in claim 10 includes through silicon via (TSV) interconnections between each chip in said memory chip stack.
12. The system as recited in claim 10 includes said controller using said first bandwidth for said high bandwidth data transfer from said memory chip stack.
13. The system as recited in claim 10 wherein said at least one memory chip stack includes a plurality of dynamic random access memory (DRAM) chips.
14. The system as recited in claim 10 includes a silicon carrier supporting said at least one memory chip stack and includes said memory controller.
15. The system as recited in claim 14 wherein said silicon carrier includes first level custom DRAM chips of said at least one memory chip stack.
16. The system as recited in claim 10 wherein said data transfer bandwidth control includes a data transfer bandwidth control computer program product tangibly embodied on a non-transitory computer readable storage medium.
17. The system as recited in claim 10 wherein said at least one memory chip stack includes a plurality of dynamic random access memory (DRAM) chips logically arranged in three levels.