IP Library Granted Patent US 8,664,752
Granted Patent B2
US 8,664,752 · App. 13/430,347 · Granted Mar 4, 2014

Semiconductor die package and method for making the same

Inventors: Oseob Jeon (Seoul, KR); Yoonhwa Choi (Inchun, KR); Boon Huan Gooi (Penang, MY); Maria Cristina B. Estacio (Cebu, PH); David Chong (Penang, MY); Tan Teik Keng (Penang, MY); Shibaek Nam (Kyonggido, KR); Rajeev Joshi (Cupertino, CA); Chung-Lin Wu (San Jose, CA); Venkat Iyer (Cupertino, CA); Lay Yeap Lim (Penang, MY); Byoung-Ok Lee (Kyonggido, KR)
Assignee: Fairchild Semiconductor Corporation
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,664,752
App. No.
13/430,347
Granted
Mar 4, 2014
Kind
B2
Abstract

Semiconductor die packages are disclosed. An exemplary semiconductor die package includes a premolded substrate. The premolded substrate can have a semiconductor die attached to it, and an encapsulating material may be disposed over the semiconductor die.

Claims (13)

1. A semiconductor die package comprising:

a premolded substrate including a leadframe structure and a molding material, wherein the leadframe structure includes a first conductive portion, a second conductive portion, and an intermediate portion between the first conductive portion and the second conductive portion, and wherein the intermediate portion includes a cavity that electrically isolates the first conductive portion and the second conductive portion;

a semiconductor die on the premolded substrate; and

an encapsulating material covering the semiconductor die and filling the cavity between the first conductive portion and the second conductive portion.

2. The semiconductor die package of claim 1 wherein the semiconductor die comprises a power MOSFET.

3. The semiconductor die package of claim 1 wherein the semiconductor die comprises a vertical device.

4. The semiconductor die package of claim 1 wherein the semiconductor die has a first surface distal to the substrate and a second surface proximate to the substrate, wherein the package further includes wirebonds electrically coupling the first surface of the die to the substrate.

5. The semiconductor die package of claim 1 wherein the semiconductor die is directly over an insulated portion of the substrate.

6. The semiconductor die package of claim 1 wherein the semiconductor die package does not have leads extending laterally away from the encapsulating material.

7. The semiconductor die package of claim 1 wherein the cavity was formed by cutting the intermediate portion.

8. The semiconductor die package of claim 1 wherein the cavity was formed by cutting the intermediate portion using a saw, a laser, or a water jet.

9. The semiconductor die package of claim 1 wherein the attached semiconductor die overlaps with at least a portion of the first conductive portion.

10. The semiconductor die package of claim 1 wherein the leadframe structure further comprises a conductive central portion inside of a region defined by a plurality of first conductive portions.

Assignments (6)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 058871, FRAME 0799 Recorded Jun 23, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 065653/0001 →
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 040075, FRAME 0644 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0536 →
SECURITY INTEREST Recorded Nov 12, 2021
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 058871/0799 →
RELEASE OF SECURITY INTEREST Recorded Oct 28, 2021
From: DEUTSCHE BANK AG NEW YORK BRANCH
To: FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 057969/0206 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 3, 2021
From: FAIRCHILD SEMICONDUCTOR CORPORATION
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 057694/0374 →
PATENT SECURITY AGREEMENT Recorded Sep 19, 2016
From: FAIRCHILD SEMICONDUCTOR CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 040075/0644 →
Continuity (10)
Division 12823411 · Jun 25, 2010
Division 11471291 · Jun 19, 2006
Provisional Application 60753040 · Dec 21, 2005
Provisional Application 60701781 · Jul 22, 2005
Provisional Application 60702076 · Jul 22, 2005
Provisional Application 60696320 · Jun 30, 2005
Provisional Application 60696027 · Jun 30, 2005
Provisional Application 60696350 · Jun 30, 2005
Provisional Application 60696305 · Jun 30, 2005
Related Publication 20120181675A1 · Jul 19, 2012