Clock signal generation circuit

1. A clock signal generation circuit for generating a high speed clock signal having a first frequency and a low speed clock signal having a second frequency lower than the first frequency, comprising:

a first oscillation circuit for generating a first oscillation clock signal having the first frequency;

a second oscillation circuit for generating a second oscillation clock signal having the second frequency;

a frequency division circuit for generating a frequency division clock signal obtained through dividing the first oscillation clock signal; and

a clock selection circuit for outputting the first oscillation clock signal as the high speed clock signal,

wherein said clock selection circuit is configured to output the second oscillation clock signal as the low speed clock signal when the second oscillation circuit transmits the second oscillation clock signal, and

said clock selection circuit is configured to output the frequency division clock signal as the low speed clock signal when the second oscillation circuit does not transmit the second oscillation clock signal.

2. The clock signal generation circuit according to claim 1 , further comprising a third oscillation circuit for generating a third oscillation clock signal having the first frequency and a phase synchronized with that of the second oscillation clock signal, said clock selection circuit being configured to output the first oscillation clock signal as the high speed clock signal before a specific period of time is elapsed after power is turned on, said clock selection circuit being configured to output the third oscillation clock signal as the high speed clock signal after the specific period of time is elapsed and the power is turned on.

3. The clock signal generation circuit according to claim 2 , wherein said first oscillation circuit is formed of a CR (Capacitor Resistor) oscillation circuit including a capacitor and a resistor, said second oscillation circuit is formed of a ceramic oscillation circuit, and said third oscillation circuit is formed of a PLL (Phase Locked Loop) oscillation circuit.

4. The clock signal generation circuit according to claim 2 , wherein said clock selection circuit is configured to output the first oscillation clock signal as the high speed clock signal before the specific period of time is elapsed after the power is turned on, said specific period of time being from when the second oscillation circuit starts transmitting the second oscillation clock signal to when the third oscillation circuit starts transmitting the third oscillation clock signal according to the second oscillation clock signal.

5. The clock signal generation circuit according to claim 2 , wherein said third oscillation circuit is configured to generate the third oscillation clock signal having the first frequency and the phase synchronized with that of the second oscillation clock signal when the second oscillation circuit transmits the second oscillation clock signal.

6. The clock signal generation circuit according to claim 2 , wherein said third oscillation circuit is configured to generate the third oscillation clock signal having the first frequency and a phase synchronized with that of the frequency division clock signal when the second oscillation circuit does not transmit the second oscillation clock signal.