Thin-film transistor substrate and method for manufacturing the same

1. A thin-film transistor (TFT) substrate, comprising:

a base substrate, comprising:

a display area comprising a data line and a TFT,

a peripheral area comprising a common voltage line, and

a test area disposed outside of the peripheral area;

a test pad disposed in the test area and electrically connected to the data line;

a test pad line connecting the data line with the test pad and crossing the common voltage line; and

a short point disposed on the common voltage line and spaced apart from the test pad line,

wherein the short point is disposed between the test pad and another test pad.

2. The TFT substrate of claim 1 ,

wherein the short point is electrically connected to the common voltage line.

3. The TFT substrate of claim 2 , wherein the test pad line has a curved portion.

4. The TFT substrate of claim 1 , wherein the test pad is configured to receive a test signal used to test for an open electrical circuit or an electrical short of the data line.

5. The TFT substrate of claim 1 , wherein the test area is configured to be a removable area.

6. A method for manufacturing a thin-film transistor (TFT) substrate, the method comprising:

forming a common voltage line in a peripheral area of a base substrate, the base substrate comprising a display area to display an image, and a test area disposed outside of the peripheral area, the peripheral area surrounding the display area;

forming a data line disposed in the display area and a test pad line disposed in the peripheral area, and the test pad line crosses the common voltage line;

forming a test pad in the test area, wherein the test pad is connected to the test pad line; and

forming a short point disposed on the common voltage line and spaced apart from the test pad line,

wherein the short point is disposed between the test pad and another test pad.

7. The method of claim 6 ,

wherein the short point is electrically connected to the common voltage line.

8. The method of claim 6 , further comprising:

testing the data line; and

cutting, after testing the data line, the test pad line at a portion of the test pad line disposed between the data line and the test pad.

9. The method of claim 8 , wherein the test pad line is cut by at least one of an etching process and a laser radiating process.

10. The method of claim 6 , further comprising:

testing the data line; and

removing, after testing the data line, the test area.

11. A display apparatus, comprising:

a first base substrate comprising a display area, a peripheral area, a data line, a thin-film transistor (TFT), and a pixel electrode;

a common voltage line disposed in the peripheral area of the first base substrate;

a test area disposed outside of the peripheral area of the first base substrate;

a test pad disposed in the test area and electrically connected to the data line;

a test pad line crossing the common voltage line;

a second base substrate facing the first base substrate;

a common electrode disposed on the second base substrate;

a liquid crystal layer interposed between the first base substrate and the second base substrate; and

a short point disposed on the common voltage line and spaced apart from the test pad line,

wherein the short point is disposed between the test pad and another test pad.

12. The display apparatus of claim 11 , wherein the first base substrate further comprises:

a sealing member adhered to the second base substrate, the sealing member being disposed outside of the peripheral area; and

an alignment layer disposed on the pixel electrode.

13. The display apparatus of claim 12 , wherein the sealing member comprises a conductive material.

14. The display apparatus of claim 13 , wherein the sealing member electrically connects the common electrode with the short point.

15. The display apparatus of claim 12 , wherein the sealing member is spaced apart from the alignment layer.

16. The display apparatus of claim 12 , wherein the sealing member overlaps with a portion of the alignment layer.

17. The display apparatus of claim 16 , further comprising:

a conductor disposed in an overlapping area, wherein the sealing member and the alignment layer overlap each other.

18. The display apparatus of claim 11 , wherein the common voltage line and the test pad line are insulated from each other.