Semiconductor device, control method thereof and data processing system
View Patent ↗Disclosed herein is a semiconductor device comprising a global bit line, a first local bit line coupled to normal memory cells, a second local bit line coupled to redundant memory cells first and second hierarchical switches, a precharge circuit precharging the global bit line, a redundancy determination circuit determining whether or not an accessed address matches a defective address, and a control circuit. In a standby state, the global bit line and the second local bit line are precharged through the second hierarchical switch. In an active state, the first local bit line is precharged through the first hierarchical switch, subsequently when the redundancy determination circuit determines that the addresses do not match, the second hierarchical switch is inactivated to access the normal memory cells, and when the redundancy determination circuit determines that the addresses match each other, the first hierarchical switch is inactivated to access the redundant memory cells.
1. A semiconductor device comprising:
a global bit line;
a first local bit line to which normal memory cells are connected, the first local bit line corresponding to the global bit line;
a first hierarchical switch controlling an electrical connection between the global bit line and the first local bit line;
a second local bit line to which redundant memory cells replacing at least the normal memory cells are connected, the second local bit line corresponding to the global bit line;
a second hierarchical switch controlling an electrical connection between the global bit line and the second local bit line;
a precharge circuit precharging the global bit line to a predetermined voltage;
a redundancy determination circuit determining whether or not an address specifying a memory cell to be accessed matches a defective address; and
a control circuit controlling operations of the normal memory cells, the redundant memory cells, the precharge circuit and the redundancy determination circuit,
wherein the control circuit performs an operation in a standby state, in which the precharge circuit and the second hierarchical switch are activated so that the global bit line and the second local bit line are precharged to the predetermined voltage, and the first hierarchical switch is inactivated so that the first local bit line is brought into a floating state,
and the control circuit performs an active operation to access the normal memory cells, in which the first hierarchical switch is activated before receiving a determination result of the redundancy determination circuit so that the first local bit line is precharged to the predetermined voltage, subsequently when the determination result indicates that the addresses do not match each other, the first hierarchical switch is maintained active while the second hierarchical switch that has been active is inactivated and the precharge circuit is inactivated so as to access the normal memory cells, and when the determination result indicates that the addresses match each other, the first hierarchical switch that has been active is inactivated and the precharge circuit is inactivated so as to access the redundant memory cells.
2. The semiconductor device according to claim 1 , wherein in the active operation, the second hierarchical switch is maintained active before receiving the determination result.
3. The semiconductor device according to claim 2 , wherein the second hierarchical switch is maintained active when the determination result indicates that the addresses match each other.
4. The semiconductor device according to claim 3 , wherein other normal memory cells are connected to the second local bit line, in addition to the redundant memory cells.
5. The semiconductor device according to claim 4 ,
wherein the control circuit performs an active operation to access the other normal memory cells, in which
the first hierarchical switch is maintained inactive and the second hierarchical switch is maintained active regardless of the determination result,
and the other normal memory cells or the redundant memory cells are accessed instead of accessing the normal memory cells in accordance with the determination result.
6. The semiconductor device according to claim 1 ,
wherein other normal memory cells are connected to the second local bit line, in addition to the redundant memory cells, and the control circuit performs an active operation to access the other normal memory cells, in which
the first hierarchical switch is maintained inactive and the second hierarchical switch is maintained active, regardless of the determination result,
and the other normal memory cells or the redundant memory cells are accessed instead of accessing the normal memory cells in accordance with the determination result.
7. The semiconductor device according to claim 1 , wherein each of the first and second hierarchical switches comprises a transistor controlling an electrical connection between the global bit line and a corresponding one of the first and second local bit lines in response to a switch control signal applied to its gate.
8. The semiconductor device according to claim 1 , further comprising a sense amplifier coupled to the global bit line,
wherein the precharge circuit is included in the sense amplifier.
9. The semiconductor device according to claim 1 , further comprising word lines selecting the normal memory cells and redundant word lines selecting the redundant memory cells,
wherein each of the word lines and the redundant word lines is hierarchized into a main word line and a sub-word line.
10. The semiconductor device according to claim 1 , wherein no redundant memory cell replacing the normal memory cells is connected to the first local bit line.