Method of manufacturing a package
View Patent ↗Provided is an ESD protection circuit for CDM capable of preventing a high current from flowing and preventing breakage when a battery is connected with reverse polarity. The ESD protection circuit employs a circuit configuration in which transistor elements are interposed in series to OFF transistors ( 11 and 13 ) included in the ESD protection circuit for CDM so that parasitic diodes of the transistor elements are connected to parasitic diodes of the OFF transistors in a reverse direction.
1. An ESD protection circuit for a semiconductor integrated circuit comprising at least a positive power supply terminal, a negative power supply terminal, an input terminal, and an internal circuit being connected to the input terminal,
the ESD protection circuit comprising:
an N-channel transistor including a gate, a source, and a substrate each connected to the negative power supply terminal; and
a first P-channel transistor including a gate connected to the negative power supply terminal, a drain connected to a gate of the internal circuit, and a source and a substrate each connected to a drain of the N-channel transistor, the source including a P-N junction, such that a parasitic diode resides between the source and the drain that is forward biased from the drain to the source.
2. An ESD protection circuit according to claim 1 , wherein the N-channel transistor and the first P-channel transistor each have a width of 50 μm or less.
3. An ESD protection circuit for a semiconductor integrated circuit comprising at least a positive power supply terminal, a negative power supply terminal, an input terminal, and an internal circuit being connected to the input terminal,
the ESD protection circuit comprising:
a N-channel transistor including a gate, a source, and a substrate each connected to the negative power supply terminal;
a first P-channel transistor including a gate connected to the negative power supply terminal, a drain connected to a gate of the internal circuit, and a source and a substrate each connected to a drain of the N-channel transistor, the source including a P-N junction, such that a parasitic diode resides between the source and the drain that is forward biased from the drain to the source;
a second P-channel transistor including a gate connected to the positive power supply terminal and a drain connected to the gate of the internal circuit; and
a third P-channel transistor including a gate connected to the gate of the internal circuit, a drain connected to the positive power supply terminal, and a source and a substrate each connected to a source and a substrate of the second P-channel transistor, the source including a P-N junction, such that a parasitic diode resides between the source and the drain that is forward biased from the drain to the source.
4. An ESD protection circuit according to claim 3 , wherein the N-channel transistor and the first P-channel transistor each have a width of 50 μm or less.
5. An ESD protection circuit for a semiconductor integrated circuit comprising at least a positive power supply terminal, a negative power supply terminal, an input terminal, and an internal circuit being connected to the input terminal,
the ESD protection circuit comprising:
an N-channel transistor including a gate, a source, and a substrate which are connected to the negative power supply terminal;
a first P-channel transistor including a gate connected to the negative power supply terminal, a drain connected to a gate of the internal circuit, and a source and a substrate each connected to a drain of the N-channel transistor, the source including a P-N junction, such that a parasitic diode resides between the source and the drain that is forward biased from the drain to the source;
a second P-channel transistor including a gate, a source, and a substrate each connected to the positive power supply terminal; and
a third P-channel transistor including a gate, a source, and a substrate each connected to the gate of the internal circuit, and a drain connected to a drain of the second P-channel transistor, the source including a P-N junction, such that a parasitic diode resides between the source and the drain that is forward biased from the drain to the source.
6. An ESD protection circuit according to claim 5 , wherein the N-channel transistor and the first P-channel transistor each have a width of 50 μm or less.