Method of programming selection transistors for NAND flash memory
View Patent ↗Disclosed herein is a method that includes providing a non-volatile memory device which includes a plurality of cells, a plurality of selection transistors each having a gate and each coupled to associated one of the cells, and a selection line coupled in common to the gates of the selection transistors, applying a first program voltage to the selection line, and applying a second program voltage to the selection line when at least one of the selection transistors have not been shifted to a program condition.
1. A device comprising:
a non-volatile memory array including a cell and a selection transistor coupled to the cell;
a first circuit supplying first and second program voltages, the first voltage being supplied to the selection transistor in order to shift the selection transistor to a program condition, the second voltage being supplied to the selection transistor when the selection transistor has not been shifted to the program condition due the supplying of the first voltage, the second voltage being larger than the first voltage;
a first switch circuit coupled to the first selection transistor; and
a second circuit coupled to the first switch circuit and supplying one of first and second bias voltages when the first switch circuit is rendered conductive, the first bias voltage being supplied to the selection transistor in order to prevent the selection transistor from being shifted to the program condition, and the second bias voltage being supplied to the selection transistor in order to allow the selection transistor to be shifted to the program condition.
2. The device according to claim 1 , further comprising:
The second switch circuit coupled to the first selection transistor; and
a third circuit coupled to the second switch circuit and verifying whether the selection transistor has been shifted to the program condition when the second switch circuit is rendered conductive.