Methods and apparatuses for adapting buffer capacity at routers
View Patent ↗In a method for dynamic buffer adjustment at a line card of router, a current buffer occupancy at the line card is compared with at least a first buffer occupancy threshold, the first buffer occupancy threshold being calculated based on a buffer occupancy threshold parameter and a capacity of at least a first buffer memory at the line card; and an active buffer capacity is adjusted by at least one of activating and deactivating buffer memory blocks at the line card based on the comparing step, the activating including switching on the buffer memory blocks, and the deactivating including causing the buffer memory blocks to enter a sleep state.
1. A method for dynamic buffer adjustment at a line card of a router, the method comprising:
comparing a current buffer occupancy at the line card with at least a first buffer occupancy threshold, the first buffer occupancy threshold being calculated based on a buffer occupancy threshold parameter and a capacity of at least a first buffer memory at the line card; and
adjusting an active buffer capacity by at least one of activating and deactivating buffer memory blocks at the line card based on the comparing step, the activating including switching on the buffer memory blocks, and the deactivating including causing the buffer memory blocks to enter a sleep state, the active buffer capacity being a size of active buffer memory at the line card, the active buffer memory at the line card including the first buffer memory and the activated buffer memory blocks at the line card, the size of the active buffer memory at the line card being an amount of data capable of being stored in the active buffer memory at the line card, and the current buffer occupancy being an amount of data currently being stored in the active buffer memory at the line card; wherein
the first buffer memory is a first cache memory at a network processor at the line card, and
the buffer memory blocks include at least one of a second cache memory block and first bulk memory block at the line card.
2. The method of claim 1 , wherein the first buffer memory is a first cache memory at a network processor at the line card, the method further including,
buffering packet data in only the first buffer memory if the current buffer occupancy is less than the first buffer occupancy threshold.
3. The method of claim 1 , further comprising:
buffering packet data in the first cache memory and the second cache memory block if the current buffer occupancy is greater than the first buffer occupancy threshold.
4. The method of claim 1 , wherein the adjusting step comprises:
activating the second cache memory block if the current buffer occupancy is greater than the first buffer occupancy threshold.
5. The method of claim 1 , wherein the comparing step comprises:
first comparing the current buffer occupancy with the first buffer occupancy threshold; and
second comparing the current buffer occupancy with a second buffer occupancy threshold if the current buffer occupancy is greater than or equal to the first buffer occupancy threshold; and wherein
the adjusting step adjusts the active buffer capacity based on the second comparing step.
6. The method of claim 5 , wherein the adjusting step comprises:
activating the second cache memory block; and
deactivating the first bulk memory block if the current buffer occupancy is less than the second buffer occupancy threshold.
7. The method of claim 5 , wherein the adjusting step comprises:
first activating the second cache memory block; and
second activating the first bulk memory block if the current buffer occupancy is greater than or equal to the second buffer occupancy threshold.
8. The method of claim 7 , wherein the second activating step comprises:
computing an amount of first bulk memory space to be activated at the line card based on the current buffer occupancy; and
activating at least a portion of the first bulk memory block based on the computed amount of first bulk memory space.
9. The method of claim 8 , wherein the computing step comprises:
calculating a number of rows of a first bulk memory required to obtain the amount of first bulk memory space to be activated at the line card; and wherein
the second activating step activates the calculated number of rows of the first bulk memory.
10. The method of claim 7 , further comprising:
buffering packet data in the first buffer memory, the second cache memory block and the first bulk memory block if the current buffer occupancy is greater than the second buffer occupancy threshold.
11. The method of claim 5 , wherein the second buffer occupancy threshold is calculated based on the buffer occupancy threshold parameter and an aggregate of a capacity of the first cache memory and a capacity of the second cache memory block.
12. The method of claim 1 , wherein the first cache memory is an on-chip cache memory block, the second cache memory block is an off-chip cache memory block, and the first bulk memory block is an off-chip bulk memory block.
13. A line card for a router, the line card comprising:
at least a first buffer memory; and
a line card processor configured to compare a current buffer occupancy at the line card with at least a first buffer occupancy threshold, the first buffer occupancy threshold being calculated based on a buffer occupancy threshold parameter and a capacity of the first buffer memory at the line card, the line card processor being further configured to adjust an active buffer capacity by at least one of activating and deactivating buffer memory blocks at the line card based on the comparison, the activating including switching on the buffer memory blocks, and the deactivating including causing the buffer memory blocks to enter a sleep state, the active buffer capacity being a size of active buffer memory at the line card, the active buffer memory at the line card including the first buffer memory and the activated buffer memory blocks at the line card, the size of the active buffer memory at the line card being an amount of data capable of being stored in the active buffer memory at the line card, and the current buffer occupancy being an amount of data currently being stored in the active buffer memory at the line card; wherein
the first buffer memory is a first cache memory at a network processor at the line card, and
the buffer memory blocks include at least one of a second cache memory block and first bulk memory block at the line card.
14. The line card of claim 13 further comprising:
a first buffer memory block; wherein
the line card processor is further configured to at least one of activate and deactivate the first buffer memory block at the line card based on the comparison between the current buffer occupancy and the first buffer occupancy threshold.
15. The line card of claim 14 , wherein the first buffer memory block comprises:
the second cache memory block configured to buffer packet data received at the line card; and
a second cache memory controller configured to control the second cache memory block.
16. The line card of claim 15 , wherein the first buffer memory block comprises:
the first bulk memory block configured to buffer packet data received at the line card; and
a first bulk memory controller configured to control the first bulk memory block.
17. The line card of claim 14 , wherein the line card processor is further configured to compare the current buffer occupancy with a second buffer occupancy threshold if the current buffer occupancy is greater than or equal to the first buffer occupancy threshold, and to adjust the active buffer capacity based on the current buffer occupancy with the second buffer occupancy threshold.
18. The line card of claim 17 , wherein the line card processor is configured to deactivate the first bulk memory block if the current buffer occupancy is less than the second buffer occupancy threshold.
19. The line card of claim 17 , wherein the line card processor is configured to activate the first bulk memory block if the current buffer occupancy is greater than or equal to the second buffer occupancy threshold.
20. The line card of claim 19 , wherein the line card processor is further configured to compute an amount of first bulk memory space needed at the line card based on the current buffer occupancy, and activate at least a portion of the first bulk memory block based on the computed amount of first bulk memory space.