Methods and apparatus for synthesizing multi-port memory circuits
View Patent ↗Multi-port memory circuits are often required within modern digital integrated circuits to store data. Multi-port memory circuits allow multiple memory users to access the same memory cell simultaneously. Multi-port memory circuits are generally custom-designed in order to obtain the best performance or synthesized with logic synthesis tools for quick design. However, these two options for creating multi-port memory give integrated circuit designers a stark choice: invest a large amount of time and money to custom design an efficient multi-port memory system or allow logic synthesis tools to inefficiently create multi-port memory. An intermediate solution is disclosed that allows an efficient multi-port memory array to be created largely using standard circuit cell components and register transfer level hardware design language code.
1. A multi-port random access memory cell, said multi-port random access memory cell comprising:
a memory element cell, said memory element cell for storing a bit of data;
at least one write port cell, each of said write port cells comprising a tri-state buffer, outputs from each of said write port cells coupled to said memory element cell; and
at least one read port cell, each of said read port cells comprising a tri-state buffer, coupling said memory element cell to inputs of each of said read port cells;
wherein said write port cells, said memory element cell, and said read port cells are standard cells placed in a common circuit row.
2. The multi-port random access memory cell as set forth in claim 1 wherein said memory element cell comprises a bus keeper circuit.
3. The multi-port random access memory cell as set forth in claim 2 wherein said bus keeper circuit comprises a pair of inverters.
4. The multi-port random access memory cell as set forth in claim 1 wherein said memory element cell further comprises an output buffer.
5. The multi-port random access memory cell as set forth in claim 1 wherein said write port cells are controlled by horizontal write word lines.
6. The multi-port random access memory cell as set forth in claim 1 wherein said write port cells are controlled by horizontal read word lines.
7. A method of creating multi-port random access memory cell, said method comprising:
selecting a memory element cell, said memory element cell for storing a bit of data;
selecting at least one write port cell, each of said write port cells comprising a tri-state buffer;
selecting at least one read port cell, each of said read port cells comprising a tri-state buffer;
laying out said write port cells, said memory element cell, and said read port cells as standard cells placed in a common row;
coupling outputs from said write port cells to said memory element cell;
and
coupling said memory element cell to inputs of said write port cells.
8. The method of creating multi-port random access memory cell as set forth in claim 7 wherein said memory element cell comprises a bus keeper circuit.
9. The method of creating multi-port random access memory cell as set forth in claim 8 wherein said bus keeper circuit comprises a pair of inverters.
10. The method of creating multi-port random access memory cell as set forth in claim 7 wherein said memory element cell further comprises an output buffer.
11. The method of creating multi-port random access memory cell as set forth in claim 7 , wherein said plurality of write port cells are controlled by horizontal write word lines.
12. The method of creating multi-port random access memory cell as set forth in claim 7 wherein said plurality of write ports are controlled by horizontal read word lines.