IP Library Granted Patent US 8,856,609
Granted Patent B2
US 8,856,609 · App. 13/434,552 · Granted Oct 7, 2014

Accelerated cyclical redundancy check

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Quick Facts
Patent No.
US 8,856,609
App. No.
13/434,552
Granted
Oct 7, 2014
Kind
B2
Abstract

Improved strategies for a Cyclical Redundancy Check (CRC) are disclosed. A CRC check of a codeblock may be initiated by a CRC decoder before receiving all of the bits by a corresponding FEC encoder. Furthermore, an incremental CRC check with respect to the data packet without the need for requesting passed through data from higher layers.

Claims (66)

1. An apparatus, comprising:

a codeblock segmentation block configured to parse a recovered sequence of data into a plurality of segmented data blocks;

a plurality of Forward Error Correction (FEC) decoders configured to decode, in a parallel manner, the plurality of segmented data blocks in accordance with a FEC encoding scheme to provide a first plurality of decoded codeblocks; and

a plurality of Cyclical Redundancy Check (CRC) decoders, each of the CRC decoders being coupled to a corresponding one of the plurality of FEC decoders, and configured to decode, in the parallel manner, the first plurality of decoded codeblocks in accordance with a CRC encoding scheme to provide a second plurality of decoded codeblocks.

2. The apparatus of claim 1 , wherein the codeblock segmentation block is further configured to parse the recovered sequence of data in accordance with a round-robin manner.

3. The apparatus of claim 1 , wherein the FEC encoding scheme comprises at least one selected from a group consisting of:

a block encoding scheme; and

a convolutional encoding scheme.

4. The apparatus of claim 1 , wherein each of the plurality of CRC decoders is configured to decode a corresponding codeblock in the first plurality of decoded codeblocks using a least significant bit (LSB) side scheme.

5. The apparatus of claim 4 , wherein the LSB side scheme is configured to determine coefficients of a quotient polynomial Q(D) of the CRC encoding scheme for a corresponding first plurality of decoded codeblocks through an exclusive disjunction of coefficients of a received polynomial R(D) that represent a corresponding second plurality of decoded codeblocks and previous coefficients of the quotient polynomial Q(D).

6. The apparatus of claim 4 , wherein the LSB side scheme is configured to decode a corresponding first plurality of decoded codeblocks beginning with a least significant term from among the corresponding first plurality of decoded codeblocks to determine whether an error occurred during transmission of the recovered sequence of data.

7. A method for decoding a first data packet that is received with an error, the first data packet being characterized as having a plurality of data blocks, the method comprising:

decoding each of the plurality of data blocks, in parallel, in accordance with a first Cyclical Redundancy Check (CRC) of a CRC encoding scheme to determine a first set of data blocks from among the plurality of data blocks that have been received with the error;

substituting a second set of data blocks from among the plurality of data blocks that have been received without the error with dummy codeblocks;

receiving a second data packet that includes the first set of data blocks and the dummy codeblocks; and

calculating a second CRC for the second data packet.

8. The method of claim 7 , wherein the dummy codeblocks represent codeblocks containing all zeros.

9. The apparatus of claim 1 , wherein a first CRC decoder in the plurality of CRC decoders is configured to:

decode a first segmented data block in the plurality of segmented data blocks starting from a least significant bit and ending with a most significant bit to determine whether an error occurred during transmission of the first segmented data block.

10. The apparatus of claim 9 , wherein the first CRC decoder is further configured to:

initiate a termination of decoding the plurality of segmented data blocks in response to determining that the error occurred during transmission of the first segmented data block.

11. The apparatus of claim 1 , further comprising:

a codeblock concatenation block coupled to respective outputs of the plurality of CRC decoders, wherein the codeblock concatenation block is configured to:

combine the second plurality of decoded codeblocks to provide a recovered data packet; and

an acknowledgement feedback generation block configured to:

examine the recovered data packet to determine whether an error occurred during transmission,

generate feedback indicating that the recovered data packet does not contain the error in response to determining that the error did not occur during transmission of the recovered data packet, and

generate feedback indicating that the recovered data packet contains the error in response to determining that the error occurred during transmission of the recovered data packet.

12. The apparatus of claim 11 , wherein the acknowledgement feedback generation block is further configured to:

in response to determining that the error occurred during transmission of the recovered data packet:

initiate a replacement of a first portion of the recovered data packet that contains no errors with one or more dummy codeblocks, and

initiate a re-transmission request of a second portion of the recovered data packet that contains the error.

13. A device, comprising:

a signal processing block configured to:

receive a signal,

downconvert the signal, and

decode a symbol of the signal to generate a data packet; and

a parallel decoding block, wherein the parallel decoding block is configured to:

decode the data packet in a parallel manner, and wherein the parallel decoding block comprises:

a codeblock segmentation block coupled to the signal processing block, wherein the codeblock segmentation block is configured to:

separate the data packet into a plurality of segmented data blocks,

a plurality of forward error correction (FEC) decoders coupled to the codeblock segmentation block, wherein the plurality of FEC decoders are configured to:

decode the plurality of segmented data blocks using a FEC decoding scheme,

a plurality of CRC decoders coupled to respective outputs of the plurality of FEC decoders, wherein the plurality of CRC decoders are configured to:

decode the plurality of segmented data blocks using a CRC decoding scheme to provide a plurality of decoded codeblocks, and

a codeblock concatenation block coupled to respective outputs of the plurality of CRC decoders, wherein the codeblock concatenation block is configured to:

combine the plurality of decoded codeblocks to provide a recovered data packet.

14. The device of claim 13 , wherein a first CRC decoder in the plurality of CRC decoders is configured to:

decode a first segmented data block in the plurality of segmented data blocks starting from a least significant bit and ending with a most significant bit to determine whether an error occurred during transmission of the first segmented data block.

15. The device of claim 14 , wherein the first CRC decoder is further configured to:

initiate a termination of decoding the plurality of segmented data blocks in response to determining that the error occurred during transmission of the first segmented data block.

16. The device of claim 13 , further comprising:

an acknowledgement feedback generation block configured to:

examine the recovered data packet to determine whether an error occurred during transmission,

generate feedback indicating that the recovered data packet does not contain the error in response to determining that the error did not occur during transmission of the data packet, and

generate feedback indicating that the recovered data packet contains the error in response to determining that the error occurred during transmission of the data packet.

17. The device of claim 16 , wherein the acknowledgement feedback generation block is further configured to:

initiate a re-transmission request of the data packet or a portion of the data packet in response to determining that the error occurred during transmission of the data packet.

18. The device of claim 16 , wherein the acknowledgement feedback generation block is further configured to:

in response to determining that the error occurred during transmission of the data packet:

initiate a replacement of a first portion of the data packet that contains no errors with one or more dummy codeblocks, and

initiate a re-transmission request of a second portion of the data packet that contains the error.

19. The method of claim 7 , further comprising:

decoding the first set of data blocks starting from a least significant bit and ending with a most significant bit to determine whether the error occurred during transmission of the first set of data blocks.

20. The method of claim 7 , further comprising:

initiating a termination of decoding the plurality of data blocks in response to determining that the error occurred during transmission of the first set of data blocks.

Assignments (6)
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE OF THE MERGER PREVIOUSLY RECORDED ON REEL 047642 FRAME 0417. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT, Recorded Mar 6, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048521/0395 →
MERGER Recorded Oct 5, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047642/0417 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 29, 2012
From: VUMMINTALA, SHASHIDHAR; VELAYOUDAME, ARUMUGAM; SOMICHETTY, GOWRISANKAR; RAJAGOPAL, SRIRAM; SOLANKI, SANDIP; KRISHNAN, KALYANA
To: BROADCOM CORPORATION
Reel/Frame 027958/0923 →