Apparatus for electrostatic discharge protection and noise suppression in circuits
View Patent ↗An integrated circuit assembly is provided that includes an integrated circuit (IC) package substrate including a package ground rail that is divided into a plurality of segments that are electrically isolated from each other. An IC die is disposed on the IC package substrate, the IC die including a plurality of circuit blocks and an IC ground rail. The IC ground rail is divided into a plurality of segments, where each segment of the IC ground rail is coupled to another segment of the IC ground rail by one or more diodes. The plurality of circuit blocks have corresponding ground nodes electrically connected to corresponding segments of the IC ground rail. The segments of the IC ground rail are electrically coupled to corresponding segments of the package ground rail by corresponding first connections.
1. An integrated circuit (IC) assembly, comprising:
an IC package substrate including a package ground rail having a plurality of segments that are physically separated from each other;
an IC die disposed on the IC package substrate, the IC die including,
an IC ground rail having a plurality of segments, each segment of the IC ground rail coupled to another segment of the IC ground rail by one or more diodes, and each segment of the IC ground rail coupled to a corresponding segment of the package ground rail by a corresponding first connection; and
a plurality of circuit blocks, each having a corresponding ground node electrically coupled to a corresponding segment of the IC ground rail; and
a support substrate having a support ground rail, wherein the IC package substrate is disposed on the support substrate, and each segment of the package ground rail is electrically coupled to the support ground rail by a corresponding second connection;
wherein at least one segment of the IC ground rail is a metal conductor having a lower resistance than that of the first connection.
2. The IC assembly of claim 1 , wherein the one or more diodes include a pair of anti-parallel diodes.
3. The IC assembly of claim 2 , wherein the anti-parallel diodes are configured to conduct during an electrostatic discharge (ESD) event.
4. The IC assembly of claim 1 , wherein the IC package is configured to include a plurality of ICs which include respective blocks and corresponding ground nodes.
5. The IC assembly of claim 1 , wherein an interference signal from a first circuit block of the plurality of circuit blocks passes through the support ground rail before reaching a second functional block of the plurality of circuit blocks.
6. The IC assembly of claim 1 , wherein the one or more diodes are configured to conduct during an electrostatic discharge (ESD) event.
7. The IC assembly of claim 1 , wherein the one or more diodes are configured to remain open-circuited when stimulated by electronic noise generated by one or more of the plurality of circuit blocks, absent an ESD event.
8. The IC assembly of claim 1 , wherein the support ground rail is a metal conductor having a lower resistance than that of the second connection.
9. The IC assembly of claim 1 , wherein the plurality of segments in the package ground rail are electrically isolated from each other in the IC package substrate.
10. An integrated circuit (IC) assembly, comprising:
a support substrate having a support ground rail, the support ground rail comprising a plurality of segments that are physically separated from each other;
an IC package substrate disposed on the support substrate, the IC package substrate including a package ground rail of segments that are physically separated from each other and each segment of the package ground rail being electrically coupled to a corresponding support ground rail segment by a corresponding first connection; and
an IC die disposed on the IC package substrate, the IC die including an IC ground rail having a plurality of segments, each segment of the IC ground rail being coupled to another segment of the IC ground rail by one or more diodes, and each segment of the IC ground rail being coupled to a corresponding segment of the package ground rail by a corresponding second connection;
wherein the plurality of support ground rail segments are not connected by a common ground rail.
11. The IC assembly of claim 10 , wherein the IC die further comprises:
a plurality of circuit blocks, each circuit block having a corresponding ground node electrically coupled to a corresponding segment of the IC ground rail.
12. The IC assembly of claim 10 , wherein the plurality of segments in the package ground rail are electrically isolated from each other in the IC package substrate.
13. The IC assembly of claim 10 , wherein the one or more diodes are configured to conduct during an electrostatic discharge (PSI)) event.
14. The IC assembly of claim 10 , wherein the one or more diodes comprise a pair of anti-parallel diodes.
15. The IC assembly of claim 10 , wherein the plurality of support ground rail segments are electrically coupled by corresponding inductive paths.
16. The IC assembly of claim 15 , wherein the inductive paths have low reactance for direct current (DC) signals and high reactance for high frequency signals.
17. An integrated circuit (IC) assembly, comprising:
a support substrate having a support ground rail;
an IC package substrate disposed on the support substrate, the IC package substrate including a package ground rail;
an IC die disposed on the IC package substrate, the IC die including,
an IC ground rail; and
a plurality of circuit blocks, each having a corresponding ground node directly connected to the package ground rail, and wherein at least one ground node is not directly connected to the IC, ground rail.
18. The IC assembly of claim 17 , where the plurality of ground nodes are connected to respective protection diodes.
19. The IC assembly of claim 17 , wherein the package ground rail is connected to the support ground rail.