Electrical erasable programmable read-only memory and manufacturing method thereof
View Patent ↗An electrical erasable programmable read-only memory (EEPROM) including a floating transistor formed on a semiconductor substrate and a tunneling transistor formed on a semiconductor substrate and configured to erase electrons trapped in the floating transistor. The tunneling transistor has a source junction region and a drain junction region that are integrally joined by lateral diffusion. The EPROM maintains a small cell size without any additional mask process, and is useable as an MTP EEPROM because electrical erasure is enabled. In addition, the adjustment of the width of a gate constituting the tunneling transistor ensures an improved degree of freedom to adjust an erasure voltage can be enhanced.
1. An electrical erasable programmable read-only memory (EEPROM), comprising:
a floating transistor formed on a semiconductor substrate; and
a tunneling transistor formed on the semiconductor substrate and configured to erase electrons trapped in the floating transistor, wherein a gate of the tunneling transistor has a narrower width than a gate of the floating transistor,
wherein the tunneling transistor has a source junction region and a drain junction region that are integrally joined by lateral diffusion.
2. The EEPROM of claim 1 , wherein:
the gate of the floating transistor has a width between approximately 0.5 μm and 0.6 μm; and
the gate of the tunneling transistor has a width between approximately 0.16 μm and 0.2 μm.
3. The EEPROM of claim 1 , wherein the gate of the tunneling transistor has an end portion intersecting edge portions of the source junction region and the drain junction region at a preset length.
4. The EEPROM of claim 3 , wherein the preset length is between 0.16 μm and 0.2 μm.
5. A method for manufacturing an electrical erasable programmable read-only memory (EEPROM), the method comprising:
forming a floating gate and a tunneling gate on a semiconductor substrate;
forming a floating transistor by forming a source junction region and a drain junction region in contact with the floating gate; and
forming a tunneling transistor by forming a source junction region and a drain junction region integrally joined by lateral diffusion so as to be in contact with the tunneling gate, wherein a gate of the tunneling transistor has a narrower width than a gate of the floating transistor.
6. The method of claim 5 , wherein an end portion of the tunneling gate is formed to intersect edge portions of the integrally connected source junction region and drain junction region at a preset length.
7. The method of claim 5 , wherein the integrally joined source junction region and drain junction region are formed by an ion implantation process with a tilt angle between approximately 25° and 45°.
8. The method of claim 7 , wherein the ion implantation process is performed under the condition that:
an ion implantation energy used is between approximately 65 KeV and 100 KeV; and
a dose amount is between approximately 5E12/cm 2 and 1E13/cm 2 .