Semiconductor memory device having plural cell capacitors stacked on one another and manufacturing method thereof
Disclosed herein is a device that includes a semiconductor substrate having a first area, a plurality of cell transistors arranged on the first area of the semiconductor substrate, and a plurality of cell capacitors each coupled to an associated one of the cell transistors, the cell capacitors being provided so as to overlap with one another on the first area.
1. A semiconductor memory device comprising:
a semiconductor substrate having a first area;
a plurality of cell transistors arranged on the first area of the semiconductor substrate;
a plurality of cell capacitors, each of the cell capacitors including a lower electrode, an upper electrode covering the lower electrode, and a capacitor insulating film provided between the lower electrode and upper electrode, the lower electrode being electrically connected to an associated one of the cell transistors, the lower electrodes of the cell capacitors being stacked in a vertical direction so that each of the lower electrodes of the cell capacitors overlaps with other lower electrodes of other cell capacitors on the first area;
a plurality of contact plugs each penetrating the lower electrodes and extending in the vertical direction, each of the contact plugs being electrically connected to an associated one of the cell transistors; and
an insulating film provided between the contact plugs and the lower electrodes,
wherein each of the contact plugs is electrically connected to an associated different one of the lower electrodes via an opening formed in the insulating film.
2. The semiconductor memory device as claimed in claim 1 , wherein
the upper electrode includes a vertical portion extending in parallel to the vertical direction and a plurality of horizontal portions extending in parallel to a surface of the semiconductor substrate,
the lower electrodes and the horizontal portions are alternately stacked across the capacitor insulating film in the vertical direction, and
the horizontal portions are electrically connected to one another via the vertical portion.
3. A semiconductor memory device comprising:
a first transistor and a second transistor;
a first capacitor including a first lower electrode extending to a horizontal direction over the first and second transistors, a capacitor insulating film, and an upper electrode;
a second capacitor including a second lower electrode stacked over the first lower electrode, the capacitor insulating film, and the upper electrode, the second lower electrode extending to the horizontal direction and electrically isolated from the first lower electrode;
a first contact plug vertically penetrating the first lower electrode and the second lower electrode, the first contact plug electrically connecting the first lower electrode to the first transistor and electrically isolated from the second lower electrode; and
a second contact plug vertically penetrating the first lower electrode and the second lower electrode, the second contact plug electrically connecting the second lower electrode to the second transistor and electrically isolated from the first lower electrode,
wherein the upper electrode covers the first lower electrode, the second lower electrode, and intervening capacitor insulating film.
4. A semiconductor memory device comprising:
a semiconductor substrate having a first area;
a plurality of cell transistors arranged on the first area of the semiconductor substrate; and
a plurality of cell capacitors, each of the cell capacitors including an electrically separate lower electrode that is insulated from other lower electrodes, an upper electrode covering the lower electrode, and a capacitor insulating film provided between the lower electrode and upper electrode, the lower electrode being electrically connected to an associated one of the cell transistors, the lower electrodes of the cell capacitors being stacked in a vertical direction so that each of the lower electrodes of the cell capacitors overlaps with other lower electrodes of other cell capacitors on the first area.
5. The semiconductor memory device as claimed in claim 4 , wherein
the upper electrode includes a vertical portion extending in parallel to the vertical direction and a plurality of horizontal portions extending in parallel to a surface of the semiconductor substrate,
the lower electrodes and the horizontal portions are alternately stacked across the capacitor insulating film in the vertical direction, and
the horizontal portions are electrically connected to one another via the vertical portion.
6. The semiconductor memory device as claimed in claim 4 , further comprising:
a plurality of contact plugs each penetrating the lower electrodes and extending in the vertical direction, each of the contact plugs being electrically connected to an associated one of the cell transistors; and
an insulating film provided between the contact plugs and the lower electrodes,
wherein each of the contact plugs is electrically connected to an associated different one of the lower electrodes via an opening formed in the insulating film.