Array substrate and liquid crystal display apparatus having the same
View Patent ↗An array substrate includes a substrate, a switching element, a pixel electrode, and a common electrode. The substrate includes a plurality of gate lines, data lines insulated from the gate lines, and the data lines extend in a direction crossing the gate lines. The switching element is connected to the gate lines and data lines. The pixel electrode is arranged in a pixel area which is defined on the substrate, and is connected to an output electrode of the switching element. The common electrode corresponds to the pixel area and is insulated from the pixel electrode, and the common electrode has at least one first slit corresponding to the data line.
1. An array substrate, comprising:
a substrate;
a plurality of gate lines;
a plurality of data lines crossing the gate lines;
a transistor electrically connected to a first gate line and a first data line;
a pixel electrode electrically connected to the transistor, the pixel electrode disposed on the substrate;
a first common electrode insulated from the pixel electrode, overlapped with the pixel electrode, and disposed on the pixel electrode such that the pixel electrode is disposed between the first common electrode and the substrate;
a second common electrode adjacent to the first common electrode such that the first data line is disposed between the first and second common electrodes; and
a connecting portion electrically connecting the first and second common electrodes to each other,
wherein the first common electrode has at least two slits overlapped with the pixel electrode,
wherein the pixel electrode forms a continuous plane between adjacent slits of the first common electrode,
and wherein the connecting portion overlaps with at least a portion of the first data line, and is formed from a same layer as the first and second common electrodes.
2. The array substrate of claim 1 , wherein the at least two slits extend in a direction substantially parallel with the first data line.
3. The array substrate of claim 2 , wherein the connecting portion includes a first connecting portion connecting a first end of the first common electrode to a first end of the second common electrode, and a second connecting portion connecting a second end of the first common electrode to a second end of the second common electrode,
and the first connecting portion is spaced apart from the second connecting portion in the direction substantially parallel with the first data line thereby forming an opening exposing at least a portion of the first data line.
4. The array substrate of claim 3 , wherein the opening has a substantially rectangular shape.
5. The array substrate of claim 4 , wherein the opening has a first width in a direction substantially perpendicular to the first data line, and the first width of the opening is greater than a width of the first data line.
6. The array substrate of claim 5 , wherein the first width of the opening is greater than a width of each of the at least two slits.
7. The array substrate of claim 6 , wherein the opening does not overlap with the pixel electrode.
8. The array substrate of claim 1 , wherein the connecting portion includes a first connecting portion connecting a first end of the first common electrode to a first end of the second common electrode, and a second connecting portion connecting a second end of the first common electrode to a second end of the second common electrode,
and the first connecting portion is spaced apart from the second connecting portion in a direction substantially parallel with the first data line thereby forming an opening exposing at least a portion of the first data line.
9. The array substrate of claim 8 , wherein the opening has a substantially rectangular shape.
10. The array substrate of claim 9 , wherein the opening has a first width in a direction substantially perpendicular to the first data line, and the first width of the opening is greater than a width of the first data line.
11. The array substrate of claim 10 , wherein the first width of the opening is greater than a width of each of the at least two slits.
12. The array substrate of claim 11 , wherein the opening does not overlap with the pixel electrode.
13. The array substrate of claim 8 , wherein the opening has a first width in a direction substantially perpendicular to the first data line, and the first width of the opening is greater than a width of the first data line.
14. The array substrate of claim 13 , wherein the first width of the opening is greater than a width of each of the at least two slits.
15. The array substrate of claim 14 , wherein the opening does not overlap with the pixel electrode.
16. The array substrate of claim 8 , wherein the opening has a first width in a direction substantially perpendicular to the first data line, and the first width of the opening is greater than a width of each of the at least two slits.
17. The array substrate of claim 16 , wherein the opening does not overlap with the pixel electrode.
18. The array substrate of claim 8 , wherein the opening does not overlap with the pixel electrode.
19. The array substrate of claim 1 , wherein the connecting portion and the first and second common electrodes are disposed directly on a same layer.
20. An array substrate, comprising:
a substrate;
a plurality of gate lines;
a plurality of data lines crossing the gate lines;
a transistor electrically connected to a first gate line and a first data line;
a first pixel electrode electrically connected to the transistor, the first pixel electrode disposed on the substrate;
a second pixel electrode adjacent to the first pixel electrode such that the first data line is disposed between the first and second pixel electrodes, the second pixel electrode disposed on the substrate; and
a common electrode overlapped with the first and second pixel electrodes, and disposed on the first and second pixel electrodes such that the first and second pixel electrodes are disposed between the common electrode and the substrate;
wherein the common electrode has at least two slits overlapped with at least one of the first and second pixel electrodes, wherein at least one of the first and second pixel electrodes forms a continuous plane between adjacent slits of the first common electrode, and
wherein the common electrode has an opening overlapped with at least a portion of the first data line and extending in a direction substantially parallel with an extending direction of the first data line.
21. The array substrate of claim 20 , wherein the at least two slits extend in a direction substantially parallel with the first data line.
22. The array substrate of claim 21 , wherein the opening has a substantially rectangular shape.
23. The array substrate of claim 22 , wherein the opening has a first width in a direction substantially perpendicular to the first data line, and the first width of the opening is greater than a width of the first data line.
24. The array substrate of claim 23 , wherein the first width of the opening is greater than a width of each of the at least two slits.
25. The array substrate of claim 24 , wherein the opening does not overlap with the first and second pixel electrodes.
26. The array substrate of claim 20 , wherein the opening has a substantially rectangular shape.
27. The array substrate of claim 26 , wherein the opening has a first width in a direction substantially perpendicular to the first data line, and the first width of the opening is greater than a width of the first data line.
28. The array substrate of claim 27 , wherein the first width of the opening is greater than a width of each of the at least two slits.
29. The array substrate of claim 28 , wherein the opening does not overlap with the first and second pixel electrodes.
30. The array substrate of claim 20 , wherein the opening has a first width in a direction substantially perpendicular to the first data line, and the first width of the opening is greater than a width of the first data line.
31. The array substrate of claim 30 , wherein the first width of the opening is greater than a width of each of the at least two slits.
32. The array substrate of claim 31 , wherein the opening does not overlap with the first and second pixel electrodes.
33. The array substrate of claim 20 , wherein the first width of the opening is greater than a width of each of the at least two slits.
34. The array substrate of claim 33 , wherein the opening does not overlap with the first and second pixel electrodes.
35. The array substrate of claim 20 , wherein the opening does not overlap with the first and second pixel electrodes.
36. An array substrate, comprising:
a plurality of gate lines disposed on a base substrate;
a plurality of data lines crossing the gate lines;
a transistor electrically connected to a first gate line and a first data line;
a pixel electrode electrically connected to the transistor through a contact hole, and
a common electrode overlapped with the pixel electrode, and disposed between the pixel electrode and the base substrate,
wherein the common electrode has a first opening and a second opening, and the contact hole is disposed in the first opening, and the second opening overlaps the first data line.
37. The array substrate of claim 36 , wherein the pixel electrode has at least two slits overlapped with the common electrode and the common electrode forms a continuous plane between adjacent slits of the pixel electrode.
38. The array substrate of claim 37 , wherein the at least two slits extend in a direction substantially parallel with the first data line.
39. The array substrate of claim 38 , wherein an area of the first opening is a larger than an area of the contact hole.
40. The array substrate of claim 36 , wherein the at least two slits extend in a direction substantially parallel with the first data line.
41. The array substrate of claim 40 , wherein an area of the first opening is a larger than an area of the contact hole.
42. The array substrate of claim 36 , wherein an area of the first opening is a larger than an area of the contact hole.