IP Library Granted Patent US 9,311,182
Granted Patent B2
US 9,311,182 · App. 13/442,284 · Granted Apr 12, 2016

Memory management system and method

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Quick Facts
Patent No.
US 9,311,182
App. No.
13/442,284
Granted
Apr 12, 2016
Kind
B2
Abstract

A memory system and method of operating the same is described, where the memory system is used to store data in a RAIDed manner. The stored data may be retrieved, including the parity data so that the stored data is recovered when the first of either the stored data without the parity data, or the stored data from all but one memory module and the parity data, has been received. The writing of data, for low write data loads, is managed such that only one of the memory modules of a RAID stripe is being written to, or erased, during a time interval.

Claims (32)

1. A method of operating a memory system, the method comprising:

providing a memory system having a plurality of FLASH memory modules;

providing a memory controller communicating with the plurality of memory modules;

storing data as a stripe of data blocks and an error correcting code data block for the stripe of data blocks, on memory modules of the plurality of memory modules;

configuring the memory controller and the memory modules such that at least one of write or erase operations of each of the memory modules where the stripe of data is stored occurs during a substantially non-overlapping time interval with respect to at least one of write or erase operations of each of the other memory modules where the stripe of data is stored;

requesting data of the stored stripe of data blocks and the error correcting code data block, from the memory modules; and

configuring the memory controller to use the earliest of:

(a) the data in the stored stripe of data blocks, or

(b) less than all of the data in the stored stripe of data blocks and the error correcting code data block,

received by the memory controller to represent the data, without waiting for the other of either (a) or (b) to be received by the memory controller; and

outputting the data,

wherein, when using the step of (b) to represent the data, the step includes using the less than all of the data in stored stripe of data blocks and the error correcting code data block to reconstruct missing data in the stripe of stored data blocks; and, wherein the missing data is data that is in (a) and that is not in (b),

wherein the requesting step provides the requested data to the output step in a time interval of less than or equal to approximately an erase time of a NAND FLASH memory circuit of a memory module of the plurality of memory modules.

2. The method of claim 1 , further comprising:

providing a communications interface adapted to connect to an external source of data or requests for retrieving data.

3. The method of claim 1 , wherein the error correcting code data is parity data.

4. The method of claim 3 , wherein the missing data of the stripe of data blocks is computed as an exclusive-OR (XOR) of less than all of the stored data blocks of the stripe of data blocks and the parity data.

5. The method of claim 1 , wherein the memory module is at least one of an electronic circuit or a physical address range.

6. A method of operating a memory system, the method comprising:

providing a memory system having a plurality of memory modules comprising FLASH memory circuits;

providing a memory controller communicating with the plurality of memory modules;

storing data as a stripe of data blocks and an error correcting code data block for the stripe of data blocks, on memory modules of the plurality of memory modules;

requesting data of the stored stripe of data blocks and the error correcting code data block, from the memory modules; and

configuring the memory controller to use the earliest of:

(a) the data in the stored stripe of data blocks, or

(b) less than all of the data in the stored stripe of data blocks and the error correcting code data block,

received by the memory controller to represent the data, without waiting for the other of either (a) or (b) to be received by the memory controller; and

outputting the data,

wherein, when using the step of (b) to represent the data, the step includes using the less than all of the data in stored stripe of data blocks and the error correcting code data block to reconstruct missing data in the stripe of stored data blocks; and, wherein the missing data is data that is in (a) and that is not in (b),

wherein the memory controller and the memory modules are configured such that the step of outputting the data is performed in a time period of less than an erase time period of a data block of the plurality of data blocks from the time of performing the step of requesting.

7. The method of claim 6 , wherein the step of outputting the data is performed while another data block is being written to a memory module of the memory modules on which the data being read has been stored.

8. The method of claim 6 , wherein the step of outputting the data is performed while an erase operation is being performed.

Assignments (7)
CORRECTIVE ASSIGNMENT TO REMOVE US PATENT NO. 9013874 PREVIOUSLY RECORDED UNDER REEL AND FRAME 064272/0249. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Sep 17, 2024
From: VSIP HOLDINGS LLC (F/K/A VIOLIN SYSTEMS LLC)
To: INNOVATIONS IN MEMORY LLC
Reel/Frame 068998/0780 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 13, 2023
From: VSIP HOLDINGS LLC (F/K/A VIOLIN SYSTEMS LLC)
To: INNOVATIONS IN MEMORY LLC
Reel/Frame 064272/0249 →
RELEASE OF SECURITY INTEREST Recorded Jun 16, 2021
From: SILICON VALLEY BANK
To: VSIP HOLDINGS LLC (F/K/A VIOLIN SYSTEMS LLC (F/K/A VIOLIN MEMORY, INC.))
Reel/Frame 056600/0186 →
CHANGE OF NAME Recorded May 25, 2021
From: VIOLIN SYSTEMS LLC
To: VSIP HOLDINGS LLC
Reel/Frame 056366/0849 →
RELEASE OF SECURITY INTEREST Recorded Jan 29, 2018
From: SILICON VALLEY BANK
To: VIOLIN SYSTEMS LLC
Reel/Frame 044757/0242 →
CHANGE OF NAME Recorded Dec 19, 2017
From: VIOLIN MEMORY, INC.
To: VIOLIN SYSTEMS LLC
Reel/Frame 044908/0680 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 8, 2017
From: BENNETT, JON C.R.
To: VIOLIN MEMORY, INC.
Reel/Frame 044074/0531 →