Data processing apparatus and method
A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit.
1. A data processing apparatus for mapping symbols received from a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol into an output symbol stream, the data processing apparatus comprising:
a de-interleaver configured to read-into a memory the predetermined number of data symbols from the OFDM sub-carrier signals, and to read-out of the memory the data symbols into the output symbol stream to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are de-interleaved from the OFDM sub-carrier signals, and
an address generator configured to generate the set of addresses, an address being generated for each of the received data symbols for mapping the data symbol received from the OFDM sub-carrier signal into the output symbol stream, the address generator comprising
a linear feedback shift register including a predetermined number of register stages and being configured to generate a pseudo-random bit sequence in accordance with a generator polynomial,
a permutation circuit configured to receive the content of the shift register stages and to permute the order of the bits present in the register stages in accordance with a permutation code to form an address of one of the OFDM sub-carriers, and
a control unit configured in combination with an address check circuit to regenerate an address when a generated address exceeds a predetermined maximum valid address, wherein
the permutation circuit is configured to change the permutation code, which permutes the order of the bits of the register stages to form the set of addresses from one OFDM symbol to another.
2. The data processing apparatus as claimed in claim 1 , wherein the permutation circuit is configured to cycle through a sequence of different permutation codes for successive OFDM symbols.
3. The data processing apparatus as claimed in claim 1 , wherein the OFDM symbol includes pilot sub-carriers, which are configured to carry known symbols, and the predetermined maximum valid address depends on a number of the pilot sub-carrier symbols present in the OFDM symbol.
4. The data processing apparatus as claimed in claim 1 , wherein the number of sub-carriers is determined by one of a plurality of operating modes, and when operating mode provides a number of the sub-carriers which is half or less than half a maximum number of sub-carriers in the OFDM symbols of any of the operating modes, and the data symbols include first sets of data symbols received from first OFDM symbols and second sets of data symbols received from second OFDM symbols, the data processing apparatus is configured to de-interleave the first and second sets of data symbols into the output data stream in accordance with an odd interleaving process,
the odd interleaving process including:
writing the first sets of data symbols received from the sub-carriers of the first OFDM symbols into a first part of the interleaver memory in accordance with an order determined by the set of addresses generated with one of the permutation codes of the sequence,
reading out the first sets of data symbols from the first part of the interleaver memory into the output data stream in accordance with a sequential order of the first sets of input data symbols,
writing the second set of data symbols received from the sub-carriers of the second OFDM symbols into a second part of the interleaver memory in accordance with an order defined by the set of addresses generated with another of the permutation codes of the sequence, and
reading out the second sets of data symbols from the second part of the interleaver memory into the output data stream in accordance with a sequential order of the second sets of input data symbols.
5. A receiver for receiving data from Orthogonal Frequency Division Multiplexing (OFDM) modulated symbols,
the receiver being configured to receive OFDM symbols, to recover the data symbols from a predetermined number of sub-carriers of the OFDM symbols, the receiver including a data processor which is configured to map the data symbols received from the OFDM symbols into an output data stream, the data processor comprising:
a de-interleaver configured to read-into a memory the predetermined number of data symbols from the OFDM sub-carrier symbols, and to read-out of the memory the data symbols into the output symbol stream to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are de-interleaved from the OFDM sub-carrier signals, and
an address generator configured to generate the set of addresses, an address being generated for each of the received data symbols for mapping the received data symbol from the OFDM sub-carrier signal into the output symbol stream, the address generator comprising:
a linear feedback shift register including a predetermined number of register stages and being configured to generate a pseudo-random bit sequence in accordance with a generator polynomial,
a permutation circuit configured to receive the content of the shift register stages and to permute the order of the bits present in the register stages in accordance with a permutation code to form an address of one of the OFDM sub-carriers, and
a control unit configured in combination with an address check circuit to re-generate an address when a generated address exceeds a predetermined maximum valid address, wherein
the permutation circuit is configured to change the permutation code, which permutes the order of the bits of the register stages to form the set of addresses from one OFDM symbol to another.
6. The receiver as claimed in claim 5 , wherein the receiver is configured to receive data which has been modulated in accordance with a Digital Video Broadcasting standard including the Digital Video Broadcasting-Terrestrial standard, the Digital Video Broadcasting-Handheld, or the Digital Video Broadcasting-Terrestrial2 standard.
7. A method of mapping symbols received from a predetermined number of sub-carrier signals of Orthogonal Frequency Division Multiplexed (OFDM) symbols into an output symbol stream, the method comprising:
reading-into a memory the predetermined number of data symbols from the OFDM sub-carrier signals,
reading-out of the memory the data symbols into the output symbol stream to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are de-interleaved from the OFDM sub-carrier signals, and
generating the set of addresses, an address being generated for each of the received symbols for mapping the received data symbol from the OFDM sub-carrier signal into the output symbol stream, the generating the set of addresses comprising:
using a linear feedback shift register including a predetermined number of register stages to generate a pseudo-random bit sequence in accordance with a generator polynomial,
using a permutation circuit to receive the content of the shift register stages and to permute the order of the bits present in the register stages in accordance with a permutation code to form an address,
re-generating an address when a generated address exceeds a predetermined maximum valid address, and
changing, by the permutation circuit, the permutation code, which permutes the order of the bits of the register stages to form the set of addresses from one OFDM symbol to another.
8. The method as claimed in claim 7 , wherein the changing the permutation code includes cycling through a sequence of different permutation codes for successive OFDM symbols.
9. The method as claimed in claim 7 , wherein the OFDM symbol includes pilot sub-carriers, which are configured to carry known symbols, and the predetermined maximum valid address depends on a number of the pilot sub-carrier symbols present in the OFDM symbol.
10. The method as claimed in claim 7 , wherein the number of sub-carriers is determined by one of a plurality of operating modes, and when the and when operating mode provides a number of sub-carriers which is half or less than half a maximum number of sub-carriers in the OFDM symbols of any of the operating modes, and the data symbols include first sets of data symbols received from first OFDM symbols and second sets of data symbols received from second OFDM symbols, and the reading-into the memory the predetermined number of data symbols from the OFDM sub-carrier signals, and the reading-out of the memory the data symbols into the output symbol stream is in accordance with an odd interleaving process, the odd interleaving process including:
writing the first sets of data symbols received from the sub-carriers of the first OFDM symbols into a first part of the interleaver memory in accordance with an order determined by the set of addresses generated with one of the permutation codes of the sequence,
reading out the first sets of data symbols from the first part of the interleaver memory into the output data stream in accordance with a sequential order of the first sets of input data symbols,
writing the second set of data symbols received from the sub-carriers of the second OFDM symbols into a second part of the interleaver memory in accordance with an order defined by the set of addresses generated with another of the permutation codes of the sequence, and
reading out the second sets of data symbols from the second part of the interleaver memory into the output data stream in accordance with a sequential order of the second sets of input data symbols.