Thin film transistor array panel and method for manufacturing the same

1. A thin film transistor substrate comprising:

an insulation substrate;

a gate line formed on the insulation substrate, wherein the gate line includes a copper layer;

a first interlayer insulating layer formed on the gate line;

a data line and a gate electrode formed on the first interlayer insulating layer;

a gate insulating layer formed on the data line and gate electrode;

a semiconductor formed on the gate insulating layer and overlapping the gate electrode, wherein the semiconductor is made of an oxide semiconductor;

a second interlayer insulating layer formed on the semiconductor;

a first connection formed on the second interlayer insulating layer and electrically connecting the gate line and the gate electrode to each other;

a drain electrode connected to the semiconductor;

a pixel electrode connected to the drain electrode;

a second connection connecting the data line and the semiconductor to each other; and

a storage electrode line formed on the insulation substrate and parallel to the gate line.

2. The thin film transistor substrate of claim 1 , wherein the storage electrode line includes a plurality of protrusions extending from the storage electrode line.

3. The thin film transistor substrate of claim 1 , further comprising a capacitive conductor formed on the first interlayer insulating layer and connected to the storage electrode line.

4. The thin film transistor substrate of claim 3 , further comprising a third connection formed on the second interlayer insulating layer and connecting the storage electrode line and the capacitive conductor to each other.

5. The thin film transistor substrate of claim 4 , wherein the third connection is made of a same material as the pixel electrode.