SELF CONTACTING BIT LINE TO MRAM CELL
Embodiments of the invention disclose magnetic memory cell configurations in which a magnetic storage structure is coupled to an upper metal layer with minimal overlay margin. This greatly reduces a size of the memory cell.
1 . A magnetic memory cell, comprising:
a memory element; and
an upper metal layer; wherein the memory element is directly coupled to the upper metal layer without the use of a via.
2 . The magnetic memory cell of claim 1 , wherein the memory element comprises a Magnetic Tunnel Junction (MTJ) stack.
3 . The magnetic memory cell of claim 2 , wherein a size of the MTJ stack is f and a width of the upper metal layer is f+2∂, where ∂ is an overlay margin for the upper metal layer.
4 . The magnetic memory cell of claim 2 , further comprising dielectric sidewalls formed on opposed sides of the MTJ stack.
5 . The magnetic memory cell of claim 1 , further comprising: a hard mask layer etched and patterned to sit atop the memory element.
6 . The magnetic memory cell of claim 5 , wherein the memory element comprises a Magnetic Tunnel Junction (MTJ) stack.
7 . The magnetic memory cell of claim 5 , wherein a size of the MTJ stack is f and a width of the upper metal layer is f+2∂, where ∂ is an overlay margin for the upper metal layer.
8 . The magnetic memory cell of claim 5 , wherein the hard mask layer comprises a material selected from the group consisting of titanium nitride, titanium, aluminum, and tantalum.
9 - 11 . (canceled)
12 . A magnetic memory cell, comprising:
a magnetic memory element;
a read lead directly coupled to a lower end of the magnetic memory element;
a bit line directly coupled to an upper end of the magnetic memory element; and
a word line positioned under the magnetic memory element such that the read lead passes between the word line and the magnetic memory element.
13 . The magnetic memory cell of claim 12 , wherein a size of the magnetic storage element is f and a width of the bit line is f+2∂, where ∂ is an overlay margin for the bit line.
14 . The magnetic memory cell of claim 12 , wherein the magnetic memory element comprises a Magnetic Tunnel Junction (MTJ) stack.
15 . The magnetic memory cell of claim 13 , further comprising dielectric sidewalls formed on sides of the MTJ stack.
16 . The magnetic memory cell of claim 12 , further comprising a hard mask layer etched and patterned to sit atop the memory element.
17 . A magnetic memory cell, comprising:
a Magnetic Tunnel Junction (MTJ) stack including a plurality of layers;
a read lead directly coupled to a lower layer of the MTJ stack;
a bit line directly coupled to an upper layer of the MTJ stack; and
a word line positioned under the MTJ stack such that the read lead passes between the word line and the MTJ stack.
18 . The magnetic memory cell of claim 17 , wherein a size of the MTJ stack is f and a width of the bit line is f+2∂, where ∂ is an overlay margin for the bit line.
19 . The magnetic memory cell of claim 17 , wherein the plurality of layers of the MTJ stack comprises a pin layer, a tunnel oxide layer, and a fixed layer.
20 . The magnetic memory cell of claim 17 , further comprising dielectric sidewalls formed on sides of the MTJ stack.
21 . The magnetic memory cell of claim 17 , further comprising a hard mask layer etched and patterned to sit atop the MTJ stack.
22 . The magnetic memory cell of claim 21 , wherein a size of the MTJ stack is f and a width of the upper metal layer is f+2∂, where ∂ is an overlay margin for the upper metal layer.
23 . The magnetic memory cell of claim 21 , wherein the hard mask layer comprises a material selected from the group consisting of titanium nitride, titanium, aluminum, and tantalum.