Accessing peripheral devices

1. A system comprising:

a master device, wherein the master device is an integrated circuit (IC) device;

multiple slave devices coupled to the master device by a clock line and a single chip select line;

a frequency generator in the master device, wherein the frequency generator places a variable frequency signal on the single chip select line, wherein the single chip select line carries only frequency signals that communicate no data;

a frequency detector/comparator in each of the multiple slave devices, wherein each frequency detector/comparator in each of the multiple slave devices is coupled to the single chip select line from the master device, wherein each frequency detector/comparator in each of the multiple slave devices determines whether the variable frequency signal on the single chip select line matches a predetermined frequency for a particular slave device, and wherein the predetermined frequency is received by the particular slave device from a particular frequency strap; and

a chip select node on the particular slave device, wherein the chip select node is coupled to the frequency detector/comparator in the particular slave device, and wherein the chip select node, in response to the frequency detector/comparator determining that the variable frequency signal on the single chip select line matches the predetermined frequency for the particular slave device, is enabled to permit a data exchange session between the master device and the particular slave device.

2. The system of claim 1 , wherein the master device is a serial peripheral interface (SPI) master device, wherein the particular slave device is an SPI slave device, and wherein the data exchange session is performed over a master out slave in (MOSI) channel and a master in slave out (MISO) channel.

3. The system of claim 1 , wherein the clock line carries only a frequency signal that communicates no data.

4. The system of claim 1 , wherein the multiple slave devices comprise an analog-to-digital converter (ADC), a digital-to-analog converter (DAC), an EPROM, an EEPROM, a FLASH memory, a thermometer, and a pressure gauge.

5. The system of claim 1 , wherein the frequency generator in the master device places an unchanging clock signal on the clock line, wherein the unchanging clock signal has a frequency that is over 100 Mhz, and wherein the variable frequency signal on the single chip select line has a frequency that is less than 20 Khz.

6. A hardware description language (HDL) design structure encoded on a machine-readable data storage medium, said HDL design structure comprising elements that, when processed in a computer-aided design system, generate a machine-executable representation of a system, wherein said system comprises:

multiple slave devices coupled to the master device by a clock line and a single chip select line;

a frequency generator in the master device, wherein the frequency generator places a variable frequency signal on the single chip select line, wherein the single chip select line carries only frequency signals that communicate no data;

a frequency detector/comparator in each of the multiple slave devices, wherein each frequency detector/comparator in each of the multiple slave devices is coupled to the single chip select line from the master device, wherein each frequency detector/comparator in each of the multiple slave devices determines whether the variable frequency signal on the single chip select line matches a predetermined frequency for a particular slave device, and wherein the predetermined frequency is received by the particular slave device from a particular frequency strap; and

a chip select node on the particular slave device, wherein the chip select node is coupled to the frequency detector/comparator in the particular slave device, and wherein the chip select node, in response to the frequency detector/comparator determining that the variable frequency signal on the single chip select line matches the predetermined frequency for the particular slave device, is enabled to permit a data exchange session between the master device and the particular slave device.

7. The HDL design structure of claim 6 , wherein the master device is a serial peripheral interface (SPI) master device, wherein the particular slave device is an SPI slave device, and wherein the data exchange session is performed over a master out slave in (MOSI) channel and a master in slave out (MISO) channel.

8. The HDL design structure of claim 6 , wherein the clock line carries only a frequency signal that communicates no data.

9. A hardware-implemented method of selectively establishing a data communication session between a master device and a slave device in a hardware system, the hardware-implemented method comprising:

a master device transmitting, on a clock line, an unchanging clock signal to multiple slave devices, wherein the master device is an integrated circuit (IC) device, and wherein the multiple slave devices are peripheral chip devices in the hardware system;

the master device transmitting, on a chip select line from the master device to the multiple slave devices, a variable frequency signal that has a frequency that is less than 20 KHz;

a frequency detector/comparator in each of the multiple slave devices determining whether the variable frequency signal on the chip select line matches a predetermined frequency for a particular slave device, wherein the frequency detector/comparator is coupled to the chip select line from the master device, and wherein the predetermined frequency is received by the particular slave device from a particular frequency strap; and

the frequency detector/comparator enabling a chip select node on the particular slave device, wherein the chip select node is coupled to the frequency detector/comparator in the particular slave device, and wherein the chip select node, in response to the frequency detector/comparator determining that the variable frequency signal on the chip select line matches the predetermined frequency for the particular slave device, is enabled to permit a data exchange session between the master device and the particular slave device.

10. The hardware-implemented method of claim 9 , wherein the master device is a serial peripheral interface (SPI) master device, wherein the particular slave device is an SPI slave device, and wherein the data exchange session is performed over a master out slave in (MOSI) channel and a master in slave out (MISO) channel.

11. The hardware-implemented method of claim 9 , wherein the clock line carries only a frequency signal that communicates no data.