IP Library Granted Patent US 9,105,786
Granted Patent B2
US 9,105,786 · App. 13/446,450 · Granted Aug 11, 2015

Thermal treatment of silicon wafers useful for photovoltaic applications

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Quick Facts
Patent No.
US 9,105,786
App. No.
13/446,450
Granted
Aug 11, 2015
Kind
B2
Abstract

Efficiency of silicon photovoltaic solar cells is increased by an annealing process for immobilizing oxygen formed in Czochralski-grown silicon. The annealing process includes a short anneal in a rapid thermal annealing chamber at a high temperature, for example, greater than 1150° C. in an oxygen-containing ambient. More preferably, the wafer is rapidly cooled to less than 950° C. without an intermediate temperature hold, at which temperature oxygen does not nucleate and/or precipitate. Subsequent processing to form a photovoltaic structure is typically performed at relatively low temperatures of less than 1000° C. or even 875° C.

Claims (16)

1. A process for forming a photovoltaic solar wafer, comprising the steps of:

growing a silicon ingot by the Czochralski process;

mechanically forming a plurality of silicon wafers from the ingot;

annealing at least one of the wafers at an annealing temperature of greater than 1150° C. in an oxygen-containing ambient for a time of between 1 and 60 seconds; and

then fabricating a photovoltaic solar cell structure including a semiconductor junction in the at least one wafer at processing temperatures of less than 1000° C.

2. The process of claim 1 , further comprising cleaning the at least one wafer between the forming step and the annealing step.

3. The process of claim 1 , wherein the annealing step is performed in a rapid thermal processing chamber including a plurality of incandescent heating lamps directed at one of the at least one wafer.

4. The process of claim 1 , wherein the ambient contains a partial pressure of at least 0.76 Torr of an oxygen-containing gas.

5. The process of claim 4 , wherein the oxygen-containing gas comprises oxygen gas (O 2 ).

6. The process of claim 1 , wherein the annealing temperature is in a range of 1200 to 1275° C.

7. The process of claim 6 , further comprising the step performed between the annealing and fabricating steps of cooling the wafer from the annealing temperature to less than 1150° C. at a cooling rate of at least 20° C./s.

8. The process of claim 7 , wherein the cooling step includes no intermediate holding step during which the cooling rate is less than 20° C./s.

9. The process of claim 7 , wherein the cooling step cools the wafer to no more than 950° C.

10. The process of claim 7 , wherein the cooling step cools the wafer at a cooling rate of at least 10° C./s over all parts of a temperature range extending from the annealing temperature to less than 950° C.

11. The process of claim 1 , wherein the processing temperatures are no more than 950° C.

12. The process of claim 1 , wherein the silicon ingot has an oxygen concentration of greater than 25 ppma.

Assignments (4)
RELEASE OF SECURITY INTEREST IN PATENTS, RECORDED AT REEL 058725, FRAME 0379 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: GTAT CORPORATION, AS GRANTOR; GTAT IP HOLDING LLC, AS GRANTOR
Reel/Frame 064067/0187 →
SECURITY INTEREST Recorded Jan 21, 2022
From: GTAT CORPORATION; GTAT IP HOLDING LLC; BY: GTAT TERRA INC., ITS SOLE MEMBER
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 058725/0379 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 26, 2015
From: GT ADVANCED CZ LLC
To: GTAT IP HOLDING LLC
Reel/Frame 035034/0955 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 9, 2012
From: DELUCA, JOHN P.
To: GT ADVANCED CZ, LLC
Reel/Frame 028180/0507 →