IP Library Granted Patent US 9,029,176
Granted Patent B2
US 9,029,176 · App. 13/448,457 · Granted May 12, 2015

Solid-state imaging device and method for manufacturing the same

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Quick Facts
Patent No.
US 9,029,176
App. No.
13/448,457
Granted
May 12, 2015
Kind
B2
Abstract

The present invention achieves an optical characteristic exhibiting excellent sensitivity or the like, by increasing the opening dimension of an optical waveguide without changing the interconnection layout, so that the optical waveguide can surely be filled with a film having high refractive index. Pixel portion A of a solid-state imaging device includes photodiode PD formed on a semiconductor substrate; a first insulating film including a concave portion above photodiode PD; and a second insulating film formed on the first insulating film such that the concave portion is filled with the second insulating film. Peripheral circuit portion B of the solid-state imaging device includes an internal interconnection formed in the first insulating film and a pad electrode formed on the internal interconnection to be electrically connected to the internal interconnection. The pad electrode is formed on the second insulating film.

Claims (28)

1. A solid-state imaging device that is formed on a semiconductor substrate and that includes a pixel portion and a peripheral circuit portion, wherein

the pixel portion includes:

a photodiode that is formed on the semiconductor substrate;

a first insulating film that is formed on the semiconductor substrate and that includes a concave portion above the photodiode; and

an optical waveguide that is formed in the concave portion and that guides light to the photodiode, wherein the optical waveguide is structured with a second insulating film with which the concave portion is filled, and a portion of the second insulating film positioned on an outer side of the concave portion in the pixel portion is formed on the first insulating film and contacts the top face of the first insulating film,

the peripheral circuit portion includes:

an interconnection that is formed in one of the first insulating film and an interlayer insulating film being an identical-level layer as the first insulating film;

a pad portion that is formed on the interconnection and that is electrically connected to the interconnection; and

a third insulating film that is formed on the first insulating film in the peripheral circuit portion, wherein the pad portion is formed on the third insulating film.

2. The solid-state imaging device according to claim 1 , wherein

the second insulating film and the third insulating film are a continuous film made of an identical material.

3. The solid-state imaging device according to claim 1 , wherein

the second insulating film and the third insulating film are made of different materials, and

the third insulating film is a film made of a material lower than the second insulating film in a refractive index.

4. The solid-state imaging device according to claim 1 , wherein

the third insulating film has a refractive index smaller than 1.75.

5. The solid-state imaging device according to claim 1 , wherein

the second insulating film has a refractive index greater than 1.75.

6. The solid-state imaging device according to claim 1 , wherein

the second insulating film includes one of silicon nitride and silicon oxynitride.

7. The solid-state imaging device according to claim 1 , wherein

the second insulating film is structured with a film made up of at least two layers.

8. The solid-state imaging device according to claim 7 , wherein

a peripheral portion at a top end of the concave portion of at least a first one of the two layers of the second insulating film is formed so as to widen upward.

9. The solid-state imaging device according to claim 1 , wherein

a height of a top face of the second insulating film in the pixel portion and a height of a top face of the third insulating film in the peripheral circuit portion are identical to each other.

10. The solid-state imaging device according to claim 1 , wherein

the interconnection includes copper as its main component, and the pad portion includes aluminum as its main component.

Assignments (4)
CORRECTIVE ASSIGNMENT TO CORRECT THE ERRONEOUSLY FILED APPLICATION NUMBERS 13/384239, 13/498734, 14/116681 AND 14/301144 PREVIOUSLY RECORDED ON REEL 034194 FRAME 0143. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Dec 24, 2020
From: PANASONIC CORPORATION
To: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
Reel/Frame 056788/0362 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 27, 2020
From: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
To: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.
Reel/Frame 052755/0870 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 10, 2014
From: PANASONIC CORPORATION
To: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
Reel/Frame 034194/0143 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 26, 2012
From: YANO, HISASHI
To: PANASONIC CORPORATION
Reel/Frame 028439/0867 →