Clock signal synchronization among computers in a network
View Patent ↗Methods, apparatus, and computer program products are disclosed for clock signal synchronization among computers in a network, including designating, as a primary clock signal for all the computers in a network, a clock signal from one of the computers in the network; providing the primary clock signal, simultaneously and in parallel, from the computer whose clock signal is designated as the primary clock signal to all the other computers in the network; and providing the primary clock signal, simultaneously and in parallel, from each computer in the network to all computers in the network through multiplexers and phase locked loops, with the primary clock signal locked in phase across all the computers by a phase locked loop on each computer.
1. A method comprising:
designating an assigned priority for each computer in a network, wherein each computer in the network is directly connected to every other computer in the network via a plurality of direct data communications links, each direct data communications link coupling only two computers for data communications;
identifying, using the assigned priority for each computer in the network, a primary clock signal for all the computers in the network;
providing the primary clock signal, simultaneously and in parallel, from the computer whose clock signal is designated as the primary clock signal to all the other computers in the network via the direct data communications links between the computer whose clock signal is designated as the primary clock signal and all other computers in the network;
providing the primary clock signal, simultaneously and in parallel, from each computer in the network to all other computers in the network via the direct data communications links between each computer in the network and all other computers in the network, with the primary clock signal locked in phase across all the computers;
receiving, by a first computer in the network, the primary clock signal from a second computer in the network;
detecting by the first computer a loss of lock on the primary clock signal by a first computer's phase locked loop; and
switching, by the first computer through a multiplexer of the first computer, to receiving the primary clock signal from a third computer in the network.
2. The method of claim 1 wherein each computer has a narrow-bandwidth phase locked loop, wherein each narrow-bandwidth phase locked loop has a loop bandwidth of at least 1 hertz and not more than 10 hertz.
3. The method of claim 1 wherein designating a clock signal as a primary clock signal further comprises:
assigning to each computer in the network a different clock signal priority; and
designating, by all the computers in the network as the primary clock signal, a clock signal from the computer in the network having the highest clock signal priority.
4. The method of claim 1 wherein providing the primary clock signal, simultaneously and in parallel, from the computer whose clock signal is designated as the primary clock signal to all the other computers in the network further comprises:
fanning out the primary clock signal from an output of the multiplexer on the computer whose clock signal is designated as the primary clock signal through a phase locked loop on the computer whose clock signal is designated as the primary clock signal through a multiplicity of driver circuits and cable conductors, one driver circuit driving each such cable conductor with a fanned out primary clock signal, each driven cable conductor connected from the computer whose clock signal is designated as the primary clock signal to a separate one of the other computers in the network.
5. The method of claim 1 wherein providing the primary clock signal, simultaneously and in parallel, from each computer in the network to all computers in the network, further comprises:
fanning out the primary clock signal from an output of the multiplexer on each computer in the network through a phase locked loop on each computer in the network through a multiplicity of driver circuits and cable conductors, one driver circuit driving each such cable conductor with a fanned out primary clock signal, each driven cable conductor connected from each computer in the network to a separate one of the other computers in the network.
6. The method of claim 1 further comprising:
relocking the first computer's phase locked loop on the primary clock signal as received from the third computer.
7. The method of claim 6 wherein:
the second computer is the computer whose clock signal is designated as the primary clock signal; and
the method further comprises designating as the primary clock signal a clock signal from one of the other computers in the network.
8. An apparatus comprising logic circuitry, the logic circuitry including a computer processor and a computer memory, the logic circuitry operating the apparatus to carry out the steps of:
designating an assigned priority for each computer in a network, wherein each computer in the network is directly connected to every other computer in the network via a plurality of direct data communications links, each direct data communications link coupling only two computers for data communications;
identifying, using the assigned priority for each computer in the network, a primary clock signal for all the computers in the network;
providing the primary clock signal, simultaneously and in parallel, from the computer whose clock signal is designated as the primary clock signal to all the other computers in the network via the direct data communications links between the computer whose clock signal is designated as the primary clock signal and all other computers in the network;
providing the primary clock signal, simultaneously and in parallel, from each computer in the network to all other computers in the network via the direct data communications links between each computer in the network and all other computers in the network, with the primary clock signal locked in phase across all the computers;
receiving, by a first computer in the network, the primary clock signal from a second computer in the network;
detecting by the first computer a loss of lock on the primary clock signal by a first computer's phase locked loop; and
switching, by the first computer through a multiplexer of the first computer, to receiving the primary clock signal from a third computer in the network.
9. The apparatus of claim 8 wherein each computer has a narrow-bandwidth phase locked loop, wherein each narrow-bandwidth phase locked loop has a loop bandwidth of at least 1 hertz and not more than 10 hertz.
10. The apparatus of claim 8 wherein designating a clock signal as a primary clock signal further comprises:
assigning to each computer in the network a different clock signal priority; and
designating, by all the computers in the network as the primary clock signal, a clock signal from the computer in the network having the highest clock signal priority.
11. The apparatus of claim 8 wherein providing the primary clock signal, simultaneously and in parallel, from each computer in the network to all computers in the network, further comprises:
fanning out the primary clock signal from an output of the multiplexer on each computer in the network through a phase locked loop on each computer in the network through a multiplicity of driver circuits and cable conductors, one driver circuit driving each such cable conductor with a fanned out primary clock signal, each driven cable conductor connected from each computer in the network to a separate one of the other computers in the network.
12. The apparatus of claim 8 wherein providing the primary clock signal, simultaneously and in parallel, from each computer in the network to all computers in the network, with the primary clock signal locked in phase across all the computers, further comprises:
fanning out the primary clock signal from an output of the multiplexer on each computer in the network through a phase locked loop on each computer in the network through a multiplicity of driver circuits and cable conductors, one driver circuit driving each such cable conductor with a fanned out primary clock signal, each driven cable conductor connected from each computer in the network to a separate one of the other computers in the network.
13. The apparatus of claim 8 further comprising the logic circuitry operating the apparatus to carry out the steps of:
relocking the first computer's phase locked loop on the primary clock signal as received from the third computer.
14. The apparatus of claim 13 wherein:
the second computer is the computer whose clock signal is designated as the primary clock signal; and
the apparatus further comprises the logic circuitry operating the apparatus to carry out the step of designating as the primary clock signal a clock signal from one of the other computers in the network.
15. A computer program product embodied upon a computer-readable storage medium that is not a signal, the computer program product comprising computer program instructions capable of:
designating an assigned priority for each computer in a network, wherein each computer in the network is directly connected to every other computer in the network via a plurality of direct data communications links, each direct data communications link coupling only two computers for data communications;
identifying, using the assigned priority for each computer in the network, a primary clock signal for all the computers in the network;
providing the primary clock signal, simultaneously and in parallel, from the computer whose clock signal is designated as the primary clock signal to all the other computers in the network via the direct data communications links between the computer whose clock signal is designated as the primary clock signal and all other computers in the network;
providing the primary clock signal, simultaneously and in parallel, from each computer in the network to all other computers in the network via the direct data communications links between each computer in the network and all other computers in the network, with the primary clock signal locked in phase across all the computers;
receiving, by a first computer in the network, the primary clock signal from a second computer in the network;
detecting by the first computer a loss of lock on the primary clock signal by a first computer's phase locked loop; and
switching, by the first computer through the first computer's multiplexer, to receiving the primary clock signal from a third computer in the network.
16. The computer program product of claim 15 wherein the computer-readable storage medium comprises a recordable medium.
17. The computer program product of claim 15 wherein designating a clock signal as a primary clock signal further comprises:
assigning to each computer in the network a different clock signal priority; and
designating, by all the computers in the network as the primary clock signal, a clock signal from the computer in the network having the highest clock signal priority.
18. The computer program product of claim 15 further comprising instructions capable of:
relocking the first computer's phase locked loop on the primary clock signal as received from the third computer.
19. The computer program product of claim 18 wherein:
the second computer is the computer whose clock signal is designated as the primary clock signal; and
the computer program product further comprising instructions capable of designating as the primary clock signal a clock signal from one of the other computers in the network.