IP Library Granted Patent US 8,558,338
Granted Patent B2
US 8,558,338 · App. 13/449,369 · Granted Oct 15, 2013

Solid-state imaging device and method for manufacturing the same

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,558,338
App. No.
13/449,369
Granted
Oct 15, 2013
Kind
B2
Abstract

There are provided semiconductor substrate, ground layer formed on semiconductor substrate and having an upper surface corresponding to pixel region, the upper surface being lower than an upper surface corresponding to peripheral circuit region, a plurality of color filters disposed two-dimensionally on the upper surface corresponding to pixel region in ground layer, and partition wall provided between color filters. In a section which is orthogonal to the upper surface corresponding to pixel region in ground layer, an occupied area of partition wall provided in outer portion disposed in contact with peripheral circuit region is smaller than that of partition wall provided in central portion of pixel region.

Claims (27)

1. A solid-state imaging device comprising:

a semiconductor substrate;

a ground layer formed on the semiconductor substrate and having an upper surface corresponding to a pixel region, the upper surface being lower than an upper surface corresponding to a peripheral circuit region;

a plurality of color filters disposed two-dimensionally on the upper surface of the ground layer corresponding to the pixel region; and

a partition wall provided between the color filters,

wherein an occupied area of the partition wall provided in an outer portion of the pixel region adjacent to the peripheral circuit region is smaller than that of the partition wall provided in a central portion of the pixel region in a section which is orthogonal to the upper surface of the ground layer corresponding to the pixel region,

wherein the outer portion of the pixel region is extended along the peripheral circuit region and has a width which is equal to or greater than 1 micrometer and is equal to or smaller than 100 micrometers.

2. The solid-state imaging device according to claim 1 , wherein an area of the partition wall in the outer portion is smaller than that of the partition wall in the central portion in the section.

3. The solid-state imaging device according to claim 2 , wherein the partition wall is formed on the upper surface of the ground layer corresponding to the pixel region, and

a width of the partition wall in the outer portion of the pixel region is smaller than that of the partition wall in the central portion in the section.

4. The solid-state imaging device according to claim 2 , wherein the partition wall is formed on the upper surface of the ground layer corresponding to the pixel region, and

a height of the partition wall in the outer portion of the pixel region is smaller than that of the partition wall in the central portion of the pixel region in the section.

5. The solid-state imaging device according to claim 1 , wherein the area of the partition wall in the outer portion of the pixel region is gradually reduced toward the peripheral circuit region in the section.

6. A method for manufacturing a solid-state imaging device including a plurality of color filters and a partition wall, the color filters being disposed two-dimensionally on an upper surface of a ground layer corresponding to a pixel region, the ground layer having a structure in which the upper surface corresponding to the pixel region is lower than an upper surface corresponding to a peripheral circuit region, comprising:

a partition wall forming step of forming the partition wall in a state in which an occupied area of the partition wall provided in an outer portion of the pixel region adjacent to the peripheral circuit region is smaller than that of the partition wall provided in a central portion of the pixel region in a section which is orthogonal to the upper surface of the ground layer corresponding to the pixel region; and

a filter forming step of forming the color filter between the partition walls,

wherein the outer portion of the pixel region is extended along the peripheral circuit region and has a width which is equal to or greater than 1 micrometer and is equal to or smaller than 100 micrometers.

7. A solid-state imaging device comprising:

a semiconductor substrate;

a ground layer formed on the semiconductor substrate and having an upper surface corresponding to a pixel region, the upper surface being lower than an upper surface corresponding to a peripheral circuit region;

a plurality of color filters disposed two-dimensionally on the upper surface of the ground layer corresponding to the pixel region; and

a partition wall provided between the color filters which are present in a central portion of the pixel region excluding an outer portion of the pixel region adjacent to the peripheral circuit region,

wherein the outer portion of the pixel region is extended along the peripheral circuit region and has a width which is equal to or greater than 1 micrometer and is equal to or smaller than 100 micrometers.

8. A method for manufacturing a solid-state imaging device including a plurality of color filters and a partition wall, the color filters being disposed two-dimensionally on an upper surface of a ground layer corresponding to a pixel region, the ground layer having a structure in which the upper surface corresponding to the pixel region is lower than an upper surface corresponding to a peripheral circuit region and a partition wall, comprising:

a partition wall forming step of forming the partition walls in a central portion of the pixel region excluding an outer portion adjacent to the peripheral circuit region; and

a filter forming step of forming the color filter between the respective partition walls in the outer portion and the central portion,

wherein the outer portion of the pixel region is extended along the peripheral circuit region and has a width which is equal to or greater than 1 micrometer and is equal to or smaller than 100 micrometers.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 27, 2020
From: PANASONIC CORPORATION
To: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.
Reel/Frame 052755/0917 →