Fractional divider for avoidance of LC-VCO interference and jitter
A fractional rate LC VCO and compensating divider circuit to avoid bit-rate interference includes an LC PLL having an input for receiving a reference clock signal, an N-stage ring VCO with rotating injection having an input coupled to an output of the LC PLL and an output for providing an output clock signal, a first divider circuit having an input coupled to an output of the N-stage ring VCO and an output coupled to the LC PLL, a second divider circuit having an input coupled to the output of the LC PLL, and an M-stage reference ring PLL having an input coupled to an output of the second divider and an output coupled to the N-stage ring VCO.
1. A circuit comprising:
an LC PLL having an input for receiving a reference clock signal;
an N-stage ring VCO with rotating injection having an input coupled to an output of the LC PLL and an output for providing an output clock signal;
a first divider circuit having an input coupled to an output of the N-stage ring VCO and an output coupled to the LC PLL;
a second divider circuit having an input coupled to the output of the LC PLL; and
an M-stage reference ring PLL having an input coupled to an output of the second divider and an output coupled to the N-stage ring VCO.
2. The circuit of claim 1 wherein the LC PLL comprises a phase comparator.
3. The circuit of claim 1 wherein the N-stage ring VCO comprises a four-stage ring VCO.
4. The circuit of claim 1 wherein the first divider circuit comprises a divide by 40 divider circuit.
5. The circuit of claim 1 wherein the second divider circuit comprises a divide by 16 divider circuit.
6. The circuit of claim 1 further comprising at least one daisy-chain segment coupled to the output of the N-stage ring VCO.
7. The circuit of claim 1 wherein the N-stage ring VCO comprises a plurality of serially coupled flip-flop circuits.
8. The circuit of claim 1 wherein the N-stage ring VCO comprises a plurality of serially coupled injector multiplexer circuits.
9. The circuit of claim 8 wherein the injector multiplexer circuits each comprise a ring input.
10. The circuit of claim 8 wherein the injector multiplexer circuits each comprise an injection input.
11. The circuit of claim 8 wherein the injector multiplexer circuits each comprise a divider ring input.
12. The circuit of claim 8 wherein the injector multiplexer circuits each comprise an output.
13. The circuit of claim 8 wherein the injector multiplexer circuits each comprise a bias input.
14. The circuit of claim 8 wherein the injector multiplexer circuits each comprise at least three N-channel differential amplifier circuits.
15. The circuit of claim 1 wherein the N-stage ring VCO comprises a plurality of serially coupled main ring units.
16. The circuit of claim 15 wherein each of the main ring units each comprise a ring input.
17. The circuit of claim 15 wherein each of the main ring units each comprise a ring output.
18. The circuit of claim 15 wherein each of the main ring units each comprise coupled P-channel and N-channel differential amplifier circuits.
19. A fractional divider method for avoidance of LC-VCO interference and jitter, the method comprising:
providing an LC PLL having an input for receiving a reference clock signal;
providing an N-stage ring VCO with rotating injection having an input coupled to an output of the LC PLL and an output for providing an output clock signal;
providing a first divider circuit having an input coupled to an output of the N-stage ring VCO and an output coupled to the LC PLL;
providing a second divider circuit having an input coupled to the output of the LC PLL; and
providing an M-stage reference ring PLL having an input coupled to an output of the second divider and an output coupled to the N-stage ring VCO.
20. The method of claim 19 , wherein one of the VCOs includes a rotating injection circuit.