IP Library Patent Application 13450342
Patent Application
App. No. 13/450,342

Memory Access Latency Metering

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Quick Facts
Patent No.
US None
App. No.
13/450,342
Abstract

Memory transactions that are issued just in time have deterministic response delay. By measuring an actual delay and comparing it to an expected delay a memory scheduler can determine whether it is issuing transaction requests too early and can thereby automatically adapt the issue of transaction requests by delaying future transaction requests to be just in time.

Claims (16)

1 . A memory scheduler comprising:

a latency objective value;

a timer that measures a length of time between a memory transaction request and a corresponding response to the memory transaction request;

logic configured to compare the length of time to the latency objective value, determine that the length of time is greater than the latency objective value, and delay a following transaction request.

2 . The memory scheduler of claim 1 further comprising logic to delay the decision of the immediately successive transaction request.

3 . The scheduler of claim 1 wherein the latency objective value is stored in a writeable register.

4 . The memory scheduler of claim 1 wherein the latency objective value changes based on the length of time.

5 . A method of optimizing memory throughput, comprising:

measuring a length of time from a transaction request to a reception of a response to the transaction request;

comparing the length of time to a latency objective value;

determining that the length of time is greater than the latency objective value; and

delaying a following transaction request.

6 . The method of claim 5 further comprising delaying a decision of the following transaction request.

7 . The method of claim 5 further comprising changing the latency objective value based on the length of time.

8 . The method of claim 5 , wherein the amount of delay of the of the following transaction request is a function of the difference between the length of time and the latency objective value.

9 . The method of claim 8 , wherein the amount of delay of the following transaction request is the difference between an expected response date and an actual response date.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 18, 2013
From: ARTERIS, SAS
To: QUALCOMM TECHNOLOGIES, INC.
Reel/Frame 031437/0901 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 1, 2012
From: LECLER, JEAN-JACQUES; BOUCARD, PHILIPPE; PROUJANSKY-BELL, JONAH
To: ARTERIS S.A.
Reel/Frame 028697/0476 →