Semiconductor device having gear down mode, method of controlling same, and information processing system
Disclosed herein is a device that includes: a frequency division circuit that divides a frequency of a first clock signal to generate a second clock signal; a first logic circuit that receives a first chip select signal and the second clock signal to generate a second chip select signal; and a command generation circuit that is activated based on the second chip select signal, and generates a second command signal based on a first command signal.
1. A semiconductor device comprising:
a frequency division circuit that divides a frequency of a first clock signal to generate a second clock signal;
a first logic circuit that receives a first chip select signal and the second clock signal to generate a second chip select signal; and
a command generation circuit that is activated based on the second chip select signal, and generates a second command signal based on a first command signal,
wherein the frequency division circuit divides the frequency of the first clock signal to generate the second clock signal in a first operation mode, and fixes a logic level of the second clock signal in a second operation mode.
2. The semiconductor device as claimed in claim 1 , further comprising a mode register that selects one of the first and second operation modes.
3. The semiconductor device as claimed in claim 1 , wherein the command generation circuit generates the second command signal by decoding the first command signal.
4. The semiconductor device as claimed in claim 1 , further comprising a first latch circuit that holds the second command signal in synchronization with the first clock signal.
5. The semiconductor device as claimed in claim 1 , further comprising a second latch circuit that holds the first command signal and the first chip select signal in synchronization with the first clock signal.
6. The semiconductor device as claimed in claim 1 , further comprising a third latch circuit that holds the first command signal and the second chip select signal in synchronization with the first clock signal.
7. The semiconductor device as claimed in claim 1 , further comprising:
a clock receiver that receives an external clock signal supplied from outside of the device and outputs the first clock signal;
a chip select receiver that receives an external chip select signal supplied from outside of the device and outputs the first chip select signal; and
a command receiver that receives an external command signal supplied from outside of the device and outputs the first command signal.
8. The semiconductor device as claimed in claim 1 , further comprising:
a delay circuit that generates a third chip select signal by delaying the first chip select signal in synchronization with the first clock signal; and
a second logic circuit that receives the third chip select signal and the second clock signal to generate the second chip select signal.
9. The semiconductor device as claimed in claim 8 , wherein the delay circuit delays the first chip select signal to generate the third chip select signal in a third operation mode, and fixes a logic level of the third chip select signal in a fourth operation mode.
10. A method of controlling a semiconductor device, comprising:
dividing a frequency of a first clock signal to generate a second clock signal;
activating, in a first operation mode, a command generation circuit when both the second clock signal and a first chip select signal are activated;
activating, in a second operation mode, the command generation circuit when the first chip select signal is activated, the second clock signal being held at a fixed logic level; and
generating a second command signal by supplying a first command signal to the command generation circuit that is activated.
11. The method of controlling a semiconductor device as claimed in claim 10 , wherein the second command signal is held based on the first clock signal regardless of which of the first and second operation modes is selected.
12. The method of controlling a semiconductor device as claimed in claim 10 , wherein the first command signal and the first chip select signal are held based on the first clock signal regardless of which of the first and second operation modes is selected.
13. The method of controlling a semiconductor device as claimed in claim 10 , wherein the first command signal and the second chip select signal are held based on the first clock signal regardless of which of the first and second operation modes is selected.
14. The method of controlling a semiconductor device as claimed in claim 10 , further comprising:
generating the first clock signal based on an external clock signal supplied from outside of the device;
generating the first chip select signal based on an external chip select signal supplied from outside of the device; and
generating the first command signal based on an external command signal supplied from outside of the device.
15. The method of controlling a semiconductor device as claimed in claim 10 , wherein
the first chip select signal is delayed in synchronization with the first clock signal to generate the third chip select signal in a third operation mode, and
the command generation circuit is activated when both the third chip select signal and the second clock signal are activated.
16. The method of controlling a semiconductor device as claimed in claim 15 , wherein the third chip select signal is activated regardless of the first chip select signal in a fourth operation mode.
17. The method of controlling a semiconductor device as claimed in claim 10 , wherein either one of the first and second operation modes is selected by a mode register included in the semiconductor device.
18. An information processing system comprising:
a first semiconductor device that outputs an external clock signal, an external chip select signal, and an external command signal; and
a second semiconductor device comprising:
a clock receiver that receives the external clock signal supplied from the first semiconductor device and outputs a first clock signal;
a chip select receiver that receives the external chip select signal supplied from the first semiconductor device and outputs a first chip select signal;
a command receiver that receives the external command signal supplied from the first semiconductor device and outputs a first command signal;
a frequency division circuit that divides a frequency of the first clock signal to generate a second clock signal;
a first logic circuit that receives the first chip select signal and the second clock signal to generate a second chip select signal; and
a command generation circuit that is activated based on the second chip select signal, and generates a second command signal based on the first command signal,
wherein the first semiconductor device brings the second semiconductor device into either one of first and second operation modes, and
the frequency division circuit divides the frequency of the first clock signal to generate the second clock signal in the first operation mode, and fixes a logic level of the second clock signal in the second operation mode.
19. The method of claim 14 , wherein said first and second operation modes are directed to whether a gear down mode is activated, wherein in said gear down mode inputs for the external command signal are enabled at every n active edges of the external command signal, where n is a power of 2.
20. The method of claim 10 , wherein said second command signal is activated within a same single clock period of said first clock signal, regardless of whether said first operation mode is active or said second operation mode is active.