Thin film transistor array and method of manufacturing the same
View Patent ↗A method of manufacturing a thin film transistor array substrate includes: forming a gate pattern on a substrate; forming a first gate insulating film and a second gate insulating film on the substrate; forming a source/drain pattern and a semiconductor pattern on the substrate; forming a passivation film on the substrate; forming a photo-resist pattern on the passivation film; patterning the passivation film using the photo-resist pattern to form a passivation film pattern, the patterning of the passivation film including over-etching the passivation film to form an open region in the passivation film; forming a transparent electrode film on the substrate; removing the photo-resist pattern and a portion of the transparent electrode film on the photo-resist pattern; and forming a pixel electrode on the first gate insulating layer.
1. A method of manufacturing a thin film transistor array, the method comprising:
forming a gate pattern on a substrate;
forming a first gate insulating film on a pixel region of the substrate;
forming a second gate insulating film on the substrate;
forming a source/drain pattern and a semiconductor pattern on the substrate;
forming a passivation film on the substrate;
forming a photo-resist pattern on the passivation film;
patterning the passivation film using the photo-resist pattern to form a passivation film pattern, the patterning of the passivation film comprising over-etching the passivation film to form an open region in the passivation film defining an undercut profile beneath the photo-resist pattern above the drain electrode;
forming a transparent electrode film on the substrate;
removing the photo-resist pattern and a portion of the transparent electrode film disposed thereon; and
forming a pixel electrode directly on the first gate insulating layer.
2. The method according to claim 1 , wherein a planar shape defined by the pixel electrode is substantially the same as a planar shape defined by the open region.
3. The method according to claim 2 , wherein the thin film transistor array comprises a data line, the method further comprising forming a storage electrode in a direction substantially parallel to the data line, wherein the storage electrode includes a substantially same material as the gate pattern.
4. The method according to claim 3 , wherein
the first gate insulating film comprises silicon oxide, and
the second gate insulating film comprises silicon nitride.
5. The method according to claim 2 , wherein
the first gate insulating film comprises silicon oxide, and
the second gate insulating film comprises silicon nitride.
6. The method according to claim 1 , wherein the thin film transistor array comprises a data line, the method further comprising forming a storage electrode in a direction substantially parallel to the data line, wherein the storage electrode includes a substantially same material as the gate pattern.
7. The method according to claim 6 , wherein
the first gate insulating pattern comprises silicon oxide, and
the second gate insulating pattern comprises silicon nitride.
8. The method according to claim 1 , wherein
the first gate insulating layer pattern comprises silicon oxide, and
the second gate insulating pattern comprises silicon nitride.
9. The method according to claim 1 , wherein forming the pixel electrode directly on the first gate insulating layer includes using a lift-off method.
10. The method according to claim 1 , wherein forming the pixel electrode directly on the first gate insulating layer includes removing the transparent electrode film together with the photo-resist pattern.