IP Library Granted Patent US 9,048,366
Granted Patent B2
US 9,048,366 · App. 13/451,439 · Granted Jun 2, 2015

Methods for forming optoelectronic devices including heterojunction

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Quick Facts
Patent No.
US 9,048,366
App. No.
13/451,439
Granted
Jun 2, 2015
Kind
B2
Abstract

Embodiments generally relate to optoelectronic semiconductor devices such as photovoltaic cells. In one aspect, a method for forming a device includes forming an absorber layer made of gallium arsenide (GaAs) and having one type of doping, and forming an emitter layer made of a different material and having a higher bandgap than the absorber layer. An intermediate layer can be formed between emitter and absorber layers. A heterojunction and p-n junction are formed between the emitter layer and the absorber layer, where the p-n junction is formed at least partially within the different material at a location offset from the heterojunction. A majority of the absorber layer can be outside of a depletion region formed by the p-n junction. The p-n junction causes a voltage to be generated in the cell in response to the cell being exposed to light at a front side.

Claims (25)

1. A method for forming an optoelectronic semiconductor device, the method comprising:

forming an intermediate layer on an absorber layer, wherein the absorber layer is made of gallium arsenide (GaAs) and has only one type of doping, the intermediate layer having the same type of doping as the absorber layer; and

forming an emitter layer on the intermediate layer, wherein the emitter layer is located closer than the absorber layer to a back side of the device, the emitter layer being made of a different material than the absorber layer and having a higher bandgap than the absorber layer, wherein the intermediate layer includes the different material of the emitter layer,

wherein a heterojunction is formed between the emitter layer and the absorber layer, and wherein a p-n junction is formed between the emitter layer and the absorber layer at a location offset from the heterojunction, the p-n junction causing a voltage to be generated in the device in response to the device being exposed to light.

2. The method of claim 1 wherein the intermediate layer includes a material gradation from GaAs at a side closer to the absorber layer, to the different material of the emitter layer at a side closer to the emitter layer.

3. The method of claim 1 wherein the optoelectronic semiconductor device is a single carrier transport solar cell.

4. The method of claim 1 wherein the p-n junction is located within two depletion lengths of the heterojunction.

5. The method of claim 1 wherein the material of the emitter layer is Aluminum Gallium Arsenide (AlGaAs).

6. A method for forming a solar cell, the method comprising:

forming an absorber layer made of gallium arsenide (GaAs) and having only one type of doping;

forming an emitter layer made of a different material than the absorber layer and having a higher bandgap than the absorber layer; and

forming an intermediate layer between the absorber layer and the emitter layer, the intermediate layer having the same type of doping as the absorber layer, wherein the intermediate layer includes a material gradation from GaAs at a side closer to the absorber layer, to the different material of the emitter layer at a side closer to the emitter layer,

wherein a heterojunction is formed between the emitter layer and the absorber layer, and wherein a p-n junction is formed between the emitter layer and the absorber layer and at least partially within the different material at a location offset from the heterojunction, the p-n junction causing a voltage to be generated in the cell in response to the cell being exposed to light at a front side of the cell.

7. The method of claim 6 wherein the material of the emitter layer is Aluminum Gallium Arsenide (AlGaAs).

8. The method of claim 6 wherein the intermediate layer includes a material gradation of about 30% Aluminum 70% GaAs to about 100% GaAs, in a direction of the emitter layer to the absorber layer.

9. The method of claim 6 wherein the emitter layer is located closer than the absorber layer to a back side of the device, such that single carrier transport is provided in the device.

10. A method for forming a photovoltaic cell, the method comprising:

forming an absorber layer made of gallium arsenide (GaAs) and having only one type of doping;

forming an emitter layer made of a different material than the absorber layer and having a higher bandgap than the absorber layer;

forming an intermediate layer between the absorber layer and the emitter layer, the intermediate layer having the same type of doping as the absorber layer; and

such that a heterojunction is formed between the emitter layer and the absorber layer and a p-n junction formed between the emitter layer and the absorber layer and at least partially within the different material at a location offset from the heterojunction, wherein a majority of the absorber layer is outside of a depletion region formed by the p-n junction, the p-n junction causing a voltage to be generated in the cell in response to the cell being exposed to light at a front side of the cell.

11. The method of claim 10 wherein the p-n junction is located within two depletion lengths of the heterojunction.

12. The method of claim 10 wherein the material of the emitter layer is Aluminum Gallium Arsenide (AlGaAs).

13. The method of claim 10 wherein the offset of the p-n junction from the heterojunction is provided by an intermediate layer wherein the intermediate layer includes a material gradation from GaAs at a side closer to the absorber layer, to the different material of the emitter layer.

14. The method of claim 10 wherein the emitter layer is located closer than the absorber layer to a back side of the cell, such that single carrier transport is provided in the cell.

Assignments (10)
SECURITY INTEREST Recorded Aug 28, 2023
From: UTICA LEASECO, LLC
To: TIGER FINANCE, LLC
Reel/Frame 064731/0814 →
CORRECTIVE ASSIGNMENT TO CORRECT THE THE ASSIGNEE ADDRESS PREVIOUSLY RECORDED AT REEL: 055766 FRAME: 0279. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Aug 9, 2021
From: UTICA LEASECO, LLC SECURED PARTY
To: UTICA LEASECO, LLC ASSIGNEE
Reel/Frame 057117/0811 →
CONFIRMATION OF FORECLOSURE TRANSFER OF PATENT RIGHTS Recorded Feb 25, 2021
From: UTICA LEASECO, LLC SECURED PARTY
To: UTICA LEASECO, LLC ASSIGNEE
Reel/Frame 055766/0279 →
SECURITY INTEREST Recorded Apr 29, 2019
From: ALTA DEVICES, INC.
To: UTICA LEASECO, LLC
Reel/Frame 049027/0944 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 11, 2016
From: HANERGY GLOBAL INVESTMENT AND SALES PTE. LTD
To: ALTA DEVICES, INC.
Reel/Frame 038066/0958 →
CHANGE OF NAME Recorded Mar 4, 2016
From: HANERGY ACQUISITION SUB INC.
To: ALTA DEVICES, INC.
Reel/Frame 038006/0457 →
CHANGE OF NAME Recorded Mar 4, 2016
From: ALTA DEVICES, INC.
To: AWBSCQEMGK, INC.
Reel/Frame 038005/0990 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 4, 2016
From: ALTA DEVICES, INC.
To: HANERGY GLOBAL INVESTMENT AND SALES PTE. LTD.
Reel/Frame 038004/0078 →
RELEASE OF SECURITY INTEREST Recorded Jan 16, 2015
From: SILICON VALLEY BANK, AS COLLATERAL AGENT
To: AWBSCQEMGK, INC. (F/K/A ALTA DEVICES, INC.)
Reel/Frame 034775/0973 →
SECURITY AGREEMENT Recorded Apr 10, 2013
From: ALTA DEVICES, INC.
To: SILICON VALLEY BANK, AS AGENT
Reel/Frame 030192/0391 →