IP Library Granted Patent US 8,965,315
Granted Patent B2
US 8,965,315 · App. 13/451,991 · Granted Feb 24, 2015

Impedance circuit and method for signal transformation

Inventor: Bart Balm (Kekerdom, NL)
Assignee: EPCOS AG
H03H7/38H03F1/56H03F3/24H03H7/0153H03F2200/387
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Quick Facts
Patent No.
US 8,965,315
App. No.
13/451,991
Granted
Feb 24, 2015
Kind
B2
Abstract

An impedance circuit includes an input terminal, a first and a second capacitive arrangement and an output terminal coupled to the input terminal by a network. The network includes the first and the second capacitive arrangement. The first capacitive arrangement includes a varactor circuit having a varactor and at least one series circuit. The at least one series circuit includes a capacitor and a switch in series connection and is coupled parallel to the varactor circuit. The second capacitive arrangement comprises an additional capacitor.

Claims (14)

1. An impedance circuit, comprising:

an input terminal;

a first capacitive arrangement that comprises a varactor circuit having a varactor and a series circuit that comprises a capacitor and a switch in series connection, the series circuit coupled in parallel with the varactor circuit;

a second capacitive arrangement that comprises an additional capacitor; and

an output terminal coupled to the input terminal by a network that comprises the first capacitive arrangement and the second capacitive arrangement; and

a control circuit that controls the switch of the series circuit and controls the varactor circuit and comprising an input for receiving a control signal and an analog-to-digital converter coupled between the input of the control circuit and a control terminal of the switch of the series circuit,

wherein the analog-to-digital converter is realized as a pipe-line converter and comprises a first sub-circuit with a first comparator and a first subtraction unit and also comprises a second sub-circuit with a second comparator and a second subtraction unit such that output terminals of the first and the second comparators form an output of the analog-to-digital converter and wherein the analog-to-digital converter incorporates a generator such that an output of the second subtraction unit is connected to an output of the generator and the generator provides a generator signal that depends on a difference between the predetermined capacitance value of the first capacitive arrangement and the present capacitance value of the series circuit.

2. An impedance circuit, comprising:

an input terminal;

a first capacitive arrangement that comprises a varactor circuit having a varactor and a series circuit that comprises a capacitor and a switch in series connection, the series circuit coupled in parallel with the varactor circuit;

a second capacitive arrangement that comprises an additional capacitor;

an output terminal coupled to the input terminal by a network that comprises the first capacitive arrangement and the second capacitive arrangement; and

a control circuit configured to control the switch of the series circuit and to control the varactor circuit, the control circuit comprising an input configured to receive a control signal and an analog-to-digital converter coupled between the input of the control circuit and a control terminal of the switch of the series circuit,

wherein the analog-to-digital converter is designed as a parallel converter that comprises a first, a second and a third comparator and the control circuit comprises a generator coupled between the input of the control circuit and the varactor circuit, the generator configured to provide a generator signal that depends on the control signal and a capacitance value provided by the series circuit and wherein the generator comprises a summation unit and a subtraction unit such that the summation unit is coupled on its input side to output terminals of the first, the second and the third comparators, a first input of the subtraction unit is coupled to the input of the control circuit and a second input of the subtraction unit is connected to an output of the summation unit as well as an output of the subtraction unit forms an output of the generator.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 2, 2017
From: EPCOS AG
To: SNAPTRACK, INC.
Reel/Frame 041608/0145 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 2, 2012
From: BALM, BART
To: EPCOS AG
Reel/Frame 028714/0105 →
Continuity (2)
Continuation PCTEP2009064855 · Nov 9, 2009
Related Publication 20120286586A1 · Nov 15, 2012