Error detection within a memory
View Patent ↗Embodiments of systems and methods for detecting errors that occur in association with an access to a memory and providing an associated error status are presented herein. According to one embodiment, an access to a memory may be received, where the access comprises a request tag. A request parity is determined based on the request tag and a stored tag and a stored parity associated with the request tag are also determined. An error correction status is determined based on the stored tag and the stored parity associated with the request tag. Additionally, a parity hotness is determined by comparing the request parity and the stored parity and a tag hotness is determined by comparing the request tag and the stored tag. An error status associated with the access is determined based on the parity hotness, the tag hotness and the error correction status.
1. An error detection system in a memory, comprising:
a tag memory configured to generate a stored tag and a stored parity associated with a request tag received in association with an access to the memory;
an error detection code encoder configured to determine a request parity based on the received request tag;
Error Correction Code (ECC) detection logic coupled to the tag memory and configured to determine an error correction status based on the stored tag and the stored parity;
hotness logic coupled to the tag memory and the error detection code encoder and configured to receive the stored tag and the stored parity from the tag memory, receive the request tag, receive the request parity from the error detection code encoder, determine a parity hotness by comparing the stored parity and the request parity, and determine a tag hotness by comparing the stored tag and the request tag; and
error status logic coupled to the hotness logic and the ECC detection logic and configured to receive the parity hotness, the tag hotness and the error correction status and determine an error status based on the parity hotness, tag hotness, and the error correction status.
2. The system of claim 1 , wherein the ECC detection logic is configured to operate in parallel with the hotness logic.
3. The system of claim 2 , wherein the stored tag and the stored parity are received at the hotness logic from the tag memory when it is accessed with the request tag, and the error detection code encoder is configured to operate in parallel with an access to the tag memory.
4. The system of claim 3 , wherein the error correction status is provided on a double error flag line and a single error flag line and the error status is provided on a double error status line, a HIT/MISS line and a fault line, wherein the HIT/MISS line is set to indicate that the requested tag is located in the memory, the double bit status error line is set to indicate that a double bit error was detected with respect to the access and a fault value is set to indicate that a detected double bit error cannot be corrected.
5. The system of claim 4 , wherein the double bit status error line is set only if the double error flag line is set.
6. The system of claim 1 , wherein the hotness logic is configured to compare the request tag and the stored tag to determine a number of bits that are different between the request tag and the stored tag.
7. The system of claim 6 , wherein the hotness logic is configured to compare the request parity and the stored parity to determine a number of bits that are different between the request parity and the stored parity.
8. The system of claim 7 , wherein the tag hotness is provided to the error status logic on a tag match line, a tag one-hot line and a tag two-hot line and the parity hotness is provided to the error status logic on a parity match line, a parity one-hot line and a parity two-hot line, wherein the tag match line is set if there are no bits different between the request tag and the stored tag, the tag one-hot line is set if there is a one bit difference between the request tag and the stored tag, the tag two-hot line is set if there is a two bit difference between the request tag and the stored tag, the parity match line is set of there are no bits different between the request parity and the stored parity, the parity one-hot line is set if there is a one bit difference between the request parity and the stored parity and the parity two-hot line is set if there is a two bit difference between the request parity and the stored parity.
9. A method for error detection in a memory, the method comprising:
receiving an access to a memory, wherein the access comprises a request tag; determining a request parity based on the request tag;
retrieving a stored tag and a stored parity associated with the request tag;
determining an error correction status based on the stored tag and the stored parity associated with the request tag;
determining a parity hotness by comparing the request parity and the stored parity;
determining a tag hotness by comparing the request tag and the stored tag; and
determining an error status associated with the access based on the parity hotness, the tag hotness and the error correction status.
10. The method of claim 9 , wherein the memory is a cache and the access an access to the cache.
11. The method of claim 10 , wherein the error correction status is determined in parallel with the determination of the parity hotness and the tag hotness.
12. The method of claim 11 , wherein the request parity is determined in parallel with the determination of the stored tag and the stored parity associated with the request tag.
13. The method of claim 12 , wherein the error correction status indicates no error, a single bit error or a double bit error and the error status comprises a hit/miss value indicating if the requested tag is located in the memory, a double bit status error value indicating if a double bit error was detected with respect to the access and a fault value indicating if a detected double bit error can be corrected.
14. The method of claim 9 , wherein the request tag and the stored tag are compared to determine a number of bits that are different between the request tag and the stored tag.
15. The method of claim 14 , wherein the tag hotness indicates the number of bits that are different between the request tag and the stored tag.
16. The method of claim 15 , wherein the request parity and the stored parity are compared to determine a number of bits that are different between the request parity and the stored parity.
17. The method of claim 16 , wherein the parity hotness indicates the number of bits that are different between the request parity and the stored parity.
18. The method of claim 9 , where the double bit status error value indicate a double bit error only if the error correction status indicates a double bit error.
19. A cache system including error detection, the cache system comprising:
an error detection code encoder configured to determine a request parity based on a request tag received at a cache in association with an access;
a tag memory operating in parallel with the error detection code encoder and configured to receive the request tag and determine a stored tag and a stored parity, wherein the tag memory and the error detection code encoder are configured to operate in parallel;
ECC detection logic coupled to the tag memory and configured to receive the stored tag and the stored parity, determine an error correction status based on the stored tag and the stored parity and provide the error correction status on a single error flag line and a double error flag line;
hotness logic coupled to the error detection code encoder and the ECC detection logic, wherein the hotness logic is operating in parallel with the ECC detection logic and configured to receive the stored tag and the stored parity, receive the request tag, receive the request parity from the error detection code encoder, determine a parity hotness by comparing the stored parity and the request parity and determine a tag hotness by comparing the stored tag and the request tag, provide the tag hotness on a tag match line, a tag one-hot line and a tag two-hot line, and provide the parity hotness on a parity match line, a parity one-hot line and a parity two-hot line; and
error status logic coupled to the hotness logic and the ECC detection logic and configured to receive the parity hotness, the tag hotness and an error correction status, and determine an error status based on the parity hotness, tag hotness, and the error correction status, wherein the error status is provided on a double error status line, a HIT/MISS line and a fault line, wherein the HIT/MISS line is set to indicate that the requested tag is located in the memory, the double bit status error line is set to indicate that a double bit error was detected with respect to the access and a fault value is set to indicate that a detected double bit error cannot be corrected.
20. The cache system of claim 19 , wherein the hotness logic is configured to compare the request tag and the stored tag to determine a number of bits that are different between the request tag and the stored tag, compare the request parity and the stored parity to determine a number of bits that are different between the request parity and the stored parity and set the tag match line if there are no bits different between the request tag and the stored tag, set the tag one-hot line if there is a one bit difference between the request tag and the stored tag, set the tag two-hot line if there is a two bit difference between the request tag and the stored tag, set the parity match line if there are no bits different between the request parity and the stored parity, set the parity one-hot line if there is a one bit difference between the request parity and the stored parity and set the parity two-hot line if there is a two bit difference between the request parity and the stored parity.