Systems and methods for local iteration determination during delay processing
View Patent ↗The present invention is related to systems and methods for characterizing circuit operation, and more particularly to systems and methods for modifying a data decoding process.
1. A data processing system, the data processing system comprising:
a data decoder circuit operable to repeatedly apply a data decode algorithm to a decoder input during a first number of local iterations to yield corresponding decoded outputs; and
a local iteration determination and limiting circuit operable to:
determine a quality of each of the corresponding decoded outputs;
based at least in part on the quality of each of the corresponding decoded outputs, select a second number of local iterations; and
wherein the data decoder circuit is further operable to repeatedly re-apply the data decode algorithm to the decoder input for the second number of local iterations to yield a decoder result.
2. The data processing system of claim 1 , wherein the quality is an indication of how many unsatisfied checks remain in the respective decoded output.
3. The data processing system of claim 2 , wherein selecting the second number of local iterations includes selecting the previously performed local iteration that yielded the smallest number of unsatisfied checks.
4. The data processing system of claim 1 , wherein the data decoder circuit is a low density parity check decoder circuit.
5. The data processing system of claim 1 , wherein the data processing circuit further comprises:
a data detector circuit operable to apply a data detection algorithm to a received input to yield a detected output, wherein the decoder input is derived from the detected output.
6. The data processing system of claim 5 , wherein the data detector circuit is selected from a group consisting of: a maximum a posteriori data detector circuit, and a Viterbi algorithm data detector circuit.
7. The data processing system of claim 5 , wherein processing through both the data detector circuit and the data decoder circuit constitutes a global iteration, and wherein the processes of: determining the quality of each of the corresponding decoded outputs, selecting a second number of local iterations, and repeatedly re-applying the data decode algorithm to the decoder input for the second number of local iterations to yield the decoder result are repeatedly applied to a given data set over at least two global iterations.
8. The data processing system of claim 5 , wherein the data processing system further comprises:
an equalizer circuit operable to receive a series of digital samples and to equalize the series of digital samples to yield the received input.
9. The data processing system of claim 8 , wherein the data processing system further comprises:
an analog to digital converter circuit operable to convert an analog input into the series of digital samples.
10. The data processing system of claim 1 , wherein the data processing system is implemented as part of a device selected from a group consisting of: a storage device and a receiving device.
11. The data processing system of claim 1 , wherein the data processing system is implemented as part of an integrated circuit.
12. A method, the method comprising:
repeatedly applying a data decode algorithm to a decoder input during a first number of local iterations by a data decoder circuit to yield corresponding decoded outputs;
determining a quality of each of the corresponding decoded outputs;
based at least in part on the quality of each of the corresponding decoded outputs, selecting a second number of local iterations; and
repeatedly re-applying the data decode algorithm to the decoder input for the second number of local iterations to yield a decoder result.
13. The method of claim 12 , the method further comprising:
determining that processing of a data set has completed without correcting all errors in the data set during a first processing mode; and
based at least in part on determining that processing of a data set has completed without correcting all errors in the data set during the first processing mode, selecting a second processing mode and identifying the data set as a source of the decoder input.
14. The method of claim 12 , wherein the quality is an indication of how many unsatisfied checks remain in the respective decoded output.
15. The method of claim 14 , wherein selecting the second number of local iterations includes selecting the previously performed local iteration that yielded the smallest number of unsatisfied checks.
16. The method of claim 12 , wherein the data decode algorithm is a low density parity check decoder algorithm.
17. The method of claim 12 , wherein the method further comprises:
applying a data detection algorithm to a received input to yield a detected output, wherein the decoder input is derived from the detected output.
18. The method of claim 17 , wherein application of the data detection algorithm and the data decode algorithm constitutes a global iteration; and wherein determining the quality of each of the corresponding decoded outputs, selecting a second number of local iterations, and repeatedly re-applying the data decode algorithm to the decoder input for the second number of local iterations to yield the decoder result are repeatedly applied to a given data set over at least two global iterations.
19. A storage device, the storage device comprising:
a storage medium;
a head assembly disposed in relation to the storage medium and operable to provide a sensed signal corresponding to information on the storage medium;
a read channel circuit including:
an analog front end circuit operable to provide an analog signal corresponding to the sensed signal;
an analog to digital converter circuit operable to sample the analog signal to yield a series of digital samples;
an equalizer circuit operable to equalize the digital samples to yield a received input;
a data detector circuit operable to apply a data detection algorithm to the received input to yield a decoder input;
a data decoder circuit operable to repeatedly apply a data decode algorithm to a decoder input during a first number of local iterations to yield corresponding decoded outputs; and
a local iteration determination and limiting circuit operable to:
determine a quality of each of the corresponding decoded outputs;
based at least in part on the quality of each of the corresponding decoded outputs, select a second number of local iterations; and
wherein the data decoder circuit is further operable to repeatedly re-apply the data decode algorithm to the decoder input for the second number of local iterations to yield a decoder result.
20. The storage device of claim 19 , wherein the quality is an indication of how many unsatisfied checks remain in the respective decoded output.