High speed gallium nitride transistor devices
A low leakage current switch device ( 110 ) is provided which includes a GaN-on-Si substrate ( 11 - 13 ) covered by a passivation surface layer ( 43 ) in which a T-gate electrode with sidewall extensions ( 48 ) is formed and coated with a conformal passivation layer ( 49 ) so that the T-gate electrode sidewall extensions are spaced apart from the underlying passivation surface layer ( 43 ) by the conformal passivation layer ( 49 ).
1. A method of forming gallium nitride transistor, comprising:
providing a substrate with a gallium nitride layer covered by a passivation surface layer;
forming a mask with a first mask opening overlying the passivation surface layer;
etching the passivation surface layer using the first mask opening in the mask to expose a gate contact surface of the substrate under the first mask opening;
forming a conductive gate electrode comprising a contact base portion in contact with the gate contact surface of the substrate and gate electrode sidewall extensions that overlap with the passivation surface layer and are vertically spaced above the passivation surface layer by a vertical gap;
forming a first plurality of patterned conductor layers to define source/drain electrode layers in electrical contact with the substrate and to define one or more bottom capacitor plate layers which are electrically isolated from the substrate;
forming a conformal Al 2 O 3 passivation layer on the gate electrode after forming the first plurality of patterned conductor layers to cover exposed sidewall surfaces of the gate electrode, wherein a portion of the conformal Al 2 O 3 passivation layer is formed on a vertical sidewall of the contact base portion located below the gate electrode sidewall extensions; and
forming a second plurality of patterned conductor layers after forming the conformal Al 2 O 3 passivation layer to define additional source/drain electrode layers in ohmic contact with the source/drain electrode layers and to define one or more top capacitor plate layers which are separated from the one or more bottom capacitor plate layers by the conformal Al 2 O 3 passivation layer.
2. The method of claim 1 , where the substrate comprises an upper gallium nitride cap layer, a middle aluminum gallium nitride barrier layer, and an underlying gallium nitride buffer layer.
3. The method of claim 1 , where forming the mask comprises forming a multi-layer e-beam gate electrode resist mask overlying the passivation surface layer.
4. The method of claim 3 , where etching the mask comprises applying a low-power SF 6 reactive-ion etch (RIE) process to the multi-layer e-beam gate electrode resist mask to form a gate electrode opening with a relatively narrower contact base opening that exposes the gate contact surface of the substrate and a relatively wider gate electrode sidewall extension opening above the relatively narrower contact base opening.
5. The method of claim 4 , where the relatively wider gate electrode sidewall extension opening is formed with sloped sidewalls formed in the multi-layer e-beam gate electrode resist mask so that the gate electrode sidewall extension opening has a wider bottom portion and a narrower top portion.
6. The method of claim 1 , where forming the conductive gate electrode comprises:
forming a gate electrode mask overlying the substrate with a gate electrode mask opening positioned wholly within the first mask opening and adapted to define a gate electrode with sidewall extensions; and
depositing a conductive gate electrode material in the gate electrode mask opening to form a conductive gate electrode in contact the gate contact surface of the substrate, where the gate electrode sidewall extensions are formed to be vertically spaced apart from the passivation surface layer by a vertical gap and where a base of the conductive gate electrode is laterally separated from the passivation surface layer by a gap.
7. The method of claim 6 , where forming a gate electrode mask comprises:
forming a multi-layer e-beam gate electrode resist mask overlying the passivation surface layer; and
etching the multi-layer e-beam gate electrode resist mask to form the gate electrode mask opening with a relatively narrower base opening that exposes the gate contact surface of the substrate and a relatively wider gate electrode sidewall extension opening above the relatively narrower base opening.
8. The method of claim 6 , where forming the conformal Al 2 O 3 passivation layer comprises forming the conformal Al 2 O 3 passivation layer in the gap.
9. The method of claim 1 , where forming the conformal Al 2 O 3 passivation layer comprises forming a conformal layer of Al 2 O 3 on the gate electrode using atomic layer deposition.
10. The method of claim 9 , further comprising forming a silicon nitride layer on the conformal Al 2 O 3 passivation Al 2 O 3 layer.
11. A method for forming a gallium nitride field effect transistor device, comprising:
providing a semiconductor layer comprising a gallium nitride surface layer;
forming a mesa in the semiconductor layer, wherein the mesa is defined by an upper portion of the semiconductor layer that is thicker than a lower portion of the semiconductor layer and that is covered by the gallium nitride surface layer;
covering the mesa with a passivation surface layer;
providing a first gate mask overlying the passivation surface layer with a first mask opening located above the mesa and having a first width;
etching through a portion of the passivation surface layer exposed by the first mask opening to expose a first portion the gallium nitride surface layer, thereby defining passivation surface layer sidewalls and forming a first gate electrode opening over the gallium nitride surface layer;
forming a conductive gate electrode in contact with at least part of the exposed first portion of the gallium nitride surface layer, where the conductive gate electrode comprises a gate length contact base having a gate length and gate electrode sidewall extensions formed to be vertically spaced apart from the passivation surface layer by a minimum vertical gap distance Y GATE ;
forming a first plurality of patterned conductor layers to define source/drain electrode layers in electrical contact with the semiconductor layer and to define one or more bottom capacitor plate layers which are electrically isolated from the semiconductor layer;
forming one or more passivation layers on the conductive gate electrode using atomic layer deposition to cover exposed sidewall surfaces of the conductive gate electrode; and
forming a second plurality of patterned conductor layers to define additional source/drain electrode layers in ohmic contact with the source/drain electrode layers and to define one or more top capacitor plate layers which are separated from the one or more bottom capacitor plate layers by the one or more passivation layers.
12. The method of claim 11 , where etching through the portion of the passivation surface layer comprises forming a passivation surface layer opening having the first width to define passivation surface layer sidewalls adjacent to the first gate electrode opening, and where forming the conductive gate electrode comprises forming the gate length contact base in direct contact with the passivation surface layer sidewalls in the first gate electrode opening.
13. The method of claim 12 , where forming one or more passivation layers on the conductive gate electrode comprises forming one or more passivation layers using atomic layer deposition to cover exposed sidewall surfaces of the conductive gate electrode except where the gate length contact base is in direct contact with the passivation surface layer sidewalls.
14. The method of claim 11 , where forming the conductive gate electrode comprises:
providing a second gate mask after etching through the portion of the passivation surface layer, where the second gate mask has a second narrower mask opening positioned wholly within the first mask opening to expose a second gate electrode opening over the gallium nitride surface layer that is positioned wholly within the first gate electrode opening such that the passivation surface layer sidewalls are spaced apart from the second gate electrode opening; and
forming the conductive gate electrode in contact with the exposed second gate electrode opening, where the conductive gate electrode comprises a gate length contact base that is laterally spaced apart from the passivation surface layer sidewalls.
15. The method of claim 14 , where forming one or more passivation layers on the conductive gate electrode comprises forming one or more passivation layers using atomic layer deposition to cover exposed sidewall surfaces of the conductive gate electrode including the exposed gate length contact base that is laterally spaced apart from the passivation surface layer sidewalls.
16. A method of forming gallium nitride transistor, comprising:
providing a substrate with a gallium nitride layer covered by a passivation surface layer;
forming a mask with a first mask opening overlying the passivation surface layer;
etching the passivation surface layer using the first mask opening in the mask to expose a gate contact surface of the substrate under the first mask opening;
forming a conductive gate electrode comprising a contact base portion in contact with the gate contact surface of the substrate and gate electrode sidewall extensions that are vertically spaced above the passivation surface layer by a vertical gap;
forming a first plurality of patterned conductor layers to define source/drain electrode layers in electrical contact with the substrate and to define one or more bottom capacitor plate layers which are electrically isolated from the substrate;
forming one or more passivation layers on the gate electrode to cover exposed sidewall surfaces of the gate electrode, wherein a portion of the one or more passivation layers is formed on a vertical sidewall of the contact base portion located below the gate electrode sidewall extensions; and then
forming a second plurality of patterned conductor layers to define additional source/drain electrode layers in ohmic contact with the source/drain electrode layers and to define one or more top capacitor plate layers which are separated from the one or more bottom capacitor plate layers by the one or more passivation layers.